Scheduling and variable binding for improved testability in high level synthesis
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[1] Tai A. Ly,et al. Applying simulated evolution to high level synthesis , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Niraj K. Jha,et al. Behavioral synthesis for easy testability in data path scheduling , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.
[3] Yu-Chin Hsu,et al. A formal approach to the scheduling problem in high level synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Robert A. Walker,et al. Introduction to the Scheduling Problem , 1995, IEEE Des. Test Comput..
[5] Leon Stok,et al. Data path synthesis , 1994, Integr..
[6] Robert H. Storer,et al. Datapath synthesis using a problem-space genetic algorithm , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Niraj K. Jha,et al. Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments , 1993, 30th ACM/IEEE Design Automation Conference.
[8] Daniel Gajski,et al. Introduction to high-level synthesis , 1994, IEEE Design & Test of Computers.
[9] A. A. Ismaeel,et al. High-level synthesis of data paths for easy testability , 1995 .
[10] Pierre G. Paulin,et al. Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Christos A. Papachristou,et al. A built-in self-testing approach for minimizing hardware overhead , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.