A multi-level transmission line network approach for multi-giga hertz clock distribution

In high performance systems, process variations and fluctuations of operating environments have significant impact on the clock skew. Recently, hybrid structures of H-tree and mesh were proposed to distribute the clock signal with a balanced H-tree and lock the skew using the shunt effect of the mesh. However, in multi-giga hertz regime, the RC model (Orshansky et al., 2002) of the mesh is no longer valid. The inductance effect of the mesh can even make the skew worse. In this paper, we investigate the use of a novel architecture which incorporates multiple level transmission line shunts to distribute global clock signal. We derive the analytical expression of the skew reduction contributed by the shunt of a transmission line with the length of an integral multiple of clock wavelength. Based on the analytical skew expression, we adopt convex programming techniques to optimize the wire widths of the multi-level transmission line network. Simulation results show that the multilevel network achieves below 4ps skew for 10GHz clock rate.

[1]  Ian Galton,et al.  Clock distribution using coupled oscillators , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[2]  Chung-Kuan Cheng,et al.  A mulitple level network approach for clock skew minimization with process variations , 2004 .

[3]  C. Patrick Yue,et al.  Design of a 10GHz clock distribution network using coupled standing-wave oscillators , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[4]  Kurt Keutzer,et al.  Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[6]  Mark A. Clements,et al.  Clock distribution using cooperative ring oscillators , 1997, Proceedings Seventeenth Conference on Advanced Research in VLSI.

[7]  K.A. Jenkins,et al.  The clock distribution of the Power4 microprocessor , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[8]  K.A. Jenkins,et al.  A clock distribution network for microprocessors , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[9]  Sani R. Nassif,et al.  Models of process variations in device and interconnect , 2000 .

[10]  Madhavan Swaminathan,et al.  On the micro-architectural impact of clock distribution using multiple PLLs , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[11]  A.P. Chandrakasan,et al.  Active GHz clock network using distributed PLLs , 2000, IEEE Journal of Solid-State Circuits.

[12]  Chung-Kuan Cheng,et al.  A mulitple level network approach for clock skew minimization with process variations , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[13]  K.L. Wong,et al.  Scalable sub-10ps skew global clock distribution for a 90nm multi-GHz IA microprocessor , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[14]  John Lillis,et al.  Interconnect Analysis and Synthesis , 1999 .

[15]  Anantha Chandrakasan,et al.  Models of Process Variations in Device and Interconnect , 2001 .

[16]  Nasser A. Kurd,et al.  A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor , 2001, IEEE J. Solid State Circuits.

[17]  Madhav P. Desai,et al.  Sizing of clock distribution networks for high performance CPU chips , 1996, DAC '96.

[18]  Mattan Kamon,et al.  FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program , 1993, 30th ACM/IEEE Design Automation Conference.

[19]  Vikas Mehrotra,et al.  Modeling the effects of systematic process variation of circuit performance , 2001 .

[20]  Vernon L. Chi Salphasic Distribution of Clock Signals for Synchronous Systems , 1994, IEEE Trans. Computers.

[21]  F. Anderson,et al.  The core clock system on the next-generation ltaniumlm microprocessor , 2002 .