A Loop Gain Optimization Technique for Integer-$N$ TDC-Based Phase-Locked Loops

This paper presents a loop gain optimization technique for integer- N digital phase-locked loops with a time-to-digital converter. Due to noise filtering properties, a phase-locked loop has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the loop gain optimization technique, the digital phase-locked loops can automatically attain this loop gain in background to minimize the jitter. Theoretical analysis is presented. The stability issue and the impact of loop latency are also discussed. Finally, the analysis is compared to behavioral simulations with good agreement.

[1]  Behzad Razavi,et al.  The Role of PLLs in Future Wireline Transmitters , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Suhwan Kim,et al.  A 1.0–4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control , 2011, IEEE Journal of Solid-State Circuits.

[3]  Giovanni Marzin,et al.  2.9 A Background calibration technique to control bandwidth in digital PLLs , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[4]  Bram Nauta,et al.  Low-jitter clock multiplication: a comparison between PLLs and DLLs , 2002 .

[5]  Kyoohyun Lim,et al.  A low-noise phase-locked loop design by loop bandwidth optimization , 2000, IEEE Journal of Solid-State Circuits.

[6]  Chih-Kong Ken Yang,et al.  Methodology for on-chip adaptive jitter minimization in phase-locked loops , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[7]  Behzad Razavi,et al.  PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design , 1996 .

[8]  P. A. Blight.  The Analysis of Time Series: An Introduction , 1991 .

[9]  J. Silva-Martinez,et al.  A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy , 2013, IEEE Journal of Solid-State Circuits.

[10]  Mark Van Paemel,et al.  Analysis of a charge-pump PLL: a new model , 1994, IEEE Trans. Commun..

[11]  Salvatore Levantino.  Advanced digital phase-locked loops , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[12]  Beomsup Kim,et al.  A low-noise fast-lock phase-locked loop with adaptive bandwidth control , 2000, IEEE Journal of Solid-State Circuits.

[13]  J. W. Scott,et al.  z-domain model for discrete-time PLL's , 1988 .

[14]  Eric A. M. Klumperink,et al.  Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.