论文信息 - True Random Bit Generator Using ZCDPLL Based on TMS320C6416

True Random Bit Generator Using ZCDPLL Based on TMS320C6416

A True Random Binary Generator (TRBG) based on a zero crossing digital phase-locked loop (ZCDPLL) is proposed. In order to face the challenges of using the proposed TRBG in cryptography, the proposed TRBG is subjected to the AIS 31 test suite. The ZCDPLL operate as chaotic generator for certain loop filter gains and this has been used to generate TRBs. The generated binary sequences have a good autocorrelation and cross-correlation properties as seen from the simulation results. A prototype of TRBG using ZCDPLL has been developed through Texas Instruments TMS320C6416 DSP development kit. The proposed TRBG successfully passed the AIS 31 test suit.

Qassim Nasir

[1] W.C. Lindsey,et al. A survey of digital phase-locked loops , 1981, Proceedings of the IEEE.

[2] J. Sprott. Chaos and time-series analysis , 2001 .

[3] Ninan Sajeeth Philip,et al. Chaos for Stream Cipher , 2001, ArXiv.

[4] Donald E. Eastlake,et al. Randomness Recommendations for Security , 1994, RFC.

[5] Alessandro Trifiletti,et al. A High-Speed Oscillator-Based Truly Random Number Source for Cryptographic Applications on a Smart Card IC , 2003, IEEE Trans. Computers.

[6] K. Aihara,et al. Cryptosystems with discretized chaotic maps , 2002 .

[7] L. Kocarev,et al. Chaos-based random number generators. Part II: practical realization , 2001 .

[8] Johan A. K. Suykens,et al. True random bit generation from a double-scroll attractor , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9] Tohru Kohda,et al. Chaotic bit sequences for stream cipher cryptography and their correlation functions , 1995, Optics East.

[10] Pavol Galajda,et al. CHAOS-BASED TRUE RANDOM NUMBER GENERATOR EMBEDDED IN A MIXED-SIGNAL RECONFIGURABLE HARDWARE , 2006 .

[11] Robert A. J. Matthews,et al. On the Derivation of a "Chaotic" Encryption Algorithm , 1989, Cryptologia.

[12] Alfred Menezes,et al. Handbook of Applied Cryptography , 2018 .

[13] H. Osborne,et al. Stability Analysis of an Nth Power Digital Phase-Locked Loop - Part I: First-Order DPLL , 1980, IEEE Transactions on Communications.