Heteroepitaxy for GaAs on Nanopatterned Si (001)

An almost defect pit-free GaAs is achieved using nanopatterned Si (001). The largest nanopattern with an aspect ratio of 4.18 and the narrowest strip of around 55 nm in width are adopted in this letter. The threading dislocations, beginning from the GaAs-Si interface and moving along the facet plane to the sidewall, are interrupted within the initial epitaxial layer. With the aspect ratio increasing from 0.44 to 2.04, the etching defect pit density can be decreased from around 5.0 × 109 cm-2 to almost zero. The improvement in material quality is verified by transmission electron microscopy, photoluminescence, and X-ray diffraction studies.

[1]  M. Akiyama,et al.  Misfit and Threading Dislocations in GaAs Layers Grown on Si Substrates by MOCVD , 1987 .

[2]  T. Nishimura,et al.  Effect of Employing Positions of Thermal Cyclic Annealing and Strained-Layer Superlattice on Defect Reduction in GaAs-on-Si , 1990 .

[3]  H. Yonezu.  Control of structural defects in group III–V–N alloys grown on Si , 2002 .

[4]  G. Wang,et al.  Selective area growth of high quality InP on Si (001) substrates , 2010 .

[5]  Y. Takano,et al.  Reduction of threading dislocations by InGaAs interlayer in GaAs layers grown on Si substrates , 1998 .

[6]  Suman Datta,et al.  Ultrahigh-Speed 0 . 5 V Supply Voltage In 0 . 7 Ga 0 . 3 As Quantum-Well Transistors on Silicon Substrate , 2009 .

[7]  S. Datta,et al.  Ultrahigh-Speed 0.5 V Supply Voltage $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$ Quantum-Well Transistors on Silicon Substrate , 2007, IEEE Electron Device Letters.

[8]  M. Carroll,et al.  Defect reduction of GaAs epitaxy on Si (001) using selective aspect ratio trapping , 2007 .

[9]  Hadis Morkoç,et al.  Gallium arsenide and other compound semiconductors on silicon , 1990 .

[10]  Magnus Willander,et al.  Stresses and strains in epilayers, stripes and quantum structures of III - V compound semiconductors , 1996 .

[11]  L. Gaoa,et al.  Selective area metalorganic vapor-phase epitaxy of gallium arsenide on silicon , 2008 .

[12]  R. Chau.  Benchmarking nanotechnology for high-performance and low-power logic transistor applications , 2004 .