A 20Gb/s 0.77pJ/b VCSEL transmitter with nonlinear equalization in 32nm SOI CMOS

This paper describes an ultra-low-power VCSEL transmitter in 32nm SOI CMOS. To increase its power efficiency, the VCSEL is driven at a low bias current. The resulting nonlinearity and loss in bandwidth is modelled and compensated by a nonlinear equalization technique. The time domain optical responses for “one” and “zero” bits are used to find the optimum equalization technique. The rising and falling edges were equalized separately and the equalization delay is selected based on the bias current of the VCSEL. The transmitter achieves energy efficiency of 0.77pJ/b at 20Gb/s.

[1]  Jason T. S. Liao,et al.  Optical I/O technology for tera-scale computing , 2009, ISSCC 2009.

[2]  Jri Lee,et al.  100Gb/s ethernet chipsets in 65nm CMOS technology , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[3]  Kenichi Ohhata,et al.  Design of a 4 $\times$ 10 Gb/s VCSEL Driver Using Asymmetric Emphasis Technique in 90-nm CMOS for Optical Interconnection , 2010, IEEE Transactions on Microwave Theory and Techniques.

[4]  Azita Emami-Neyestanak,et al.  A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects , 2008, IEEE Journal of Solid-State Circuits.

[5]  Johan S. Gustavsson,et al.  High-Speed, Low-Current-Density 850 nm VCSELs , 2009 .

[6]  Yukito Tsunoda,et al.  8.9 A 40Gb/s VCSEL over-driving IC with group-delay-tunable pre-emphasis for optical interconnection , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).