Stability analysis of fourth-order charge-pump PLLs using linearized discrete-time models

In this paper, we derive state equations for linearized discrete-time models of fourth-order charge-pump phase-locked loops. We solve the differential equations of the loop filter by using the initial conditions and the boundary conditions in a period. The solved equations are linearized and rearranged as discrete-time state equations for checking stability conditions. Some behavioral simulations are performed to verify the proposed method. By examining the stability of loops with different conditions, we also propose an expression between the lower bound of the reference frequency, the open loop unit gain bandwidth, and the phase margin.

[1]  H.R. Rategh,et al.  A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver , 2000, IEEE Journal of Solid-State Circuits.

[2]  D.S. Naidu,et al.  Digital control system analysis and design , 1986, Proceedings of the IEEE.

[3]  F. Gardner,et al.  Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..

[4]  Shen-Iuan Liu,et al.  A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme , 2001 .

[5]  J. H. Mulligan,et al.  Optimization of phase-locked loop performance in data recovery systems , 1994 .

[6]  Mark Van Paemel,et al.  Analysis of a charge-pump PLL: a new model , 1994, IEEE Trans. Commun..

[7]  P. Larssom,et al.  A simulator core for charge-pump PLLs , 1998 .

[8]  Michael Peter Kennedy,et al.  Behavioral modeling of charge pump phase locked loops , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).