A 0.5-V power-efficient low-noise CMOS instrumentation amplifier for wireless biosensor

Abstract This paper presents a low-power, low-noise CMOS instrumentation amplifier intended for use in wireless bio-potential monitoring system. It employs a capacitively-coupled topology to achieve high power efficiency. In order to depress the noise, chopper-stabilized technique is used and a transconductance-boost technique is introduced in low-noise amplifier (LNA). All MOS transistors implemented in LNA are biased in subthreshold region with a supply voltage of 0.5 V to reduce the power consumption. Moreover, a DC-servo loop (DSL) is implemented to realize a high-pass corner for electrode offset cancellation. Implemented in a 0.18 μm CMOS process, the front-end circuit occupies 0.48 mm 2 and draws 1.5 μA. The capacitively-coupled chopper-stabilized instrumentation amplifier (CCIA) draws 800 nA and its input-referred noise is 3.5 μV rms integrated from 0.5 to 1 kHz, which results in a NEF of 3.8 and a PEF of 7.2 respectively. The whole circuit achieves 98 dB CMRR and 73 dB PSRR . The total input-referred noise of the front-end instrumentation amplifier including the DSL is 4.3 μV rms integrated from 0.5 to 1 kHz.

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