Resistorless switched-capacitor current reference based on the MOSFET ZTC condition

The MOSFET Zero Temperature Coefficient (ZTC) condition is a strategy that can be used to implement low temperature sensitivity circuits, such as current and voltage references. This condition is usually analyzed using the strong inversion quadratic MOSFET model. In this work we use a different approach, based on a continuous MOSFET model that can predict its behavior from weak to strong inversion. Based on this analysis, we verify that the ZTC point occurs from moderate to strong inversion for any CMOS process, since this point must occur for gate-source voltages larger than one threshold voltage. Also, a resistorless switched capacitor current reference based on the ZTC condition (ZSCCR), presenting low temperature coefficient (TC), is presented. The ZSCCR is designed in a 180 nm process, resulting a reference current of 5.88 μA under a supply voltage of 1.8 V, and occuping a silicon area around 0.010mm2. Results from circuit simulation show an effective temperature coefficient (TCeff ) of 60 ppm/°C from -45 to +85 °C and a power consumption of 63 μW.

[1]  Sergio Bampi,et al.  Self-biased CMOS current reference based on the ZTC operation condition , 2014, 2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI).

[2]  K. S. Kundert,et al.  Introduction to RF simulation and its application , 1998, Proceedings of the 1998 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.98CH36198).

[3]  Carlos Galup-Montoro,et al.  CMOS Analog Design Using All-Region MOSFET Modeling: Fundamentals of integrated continuous-time filters , 2010 .

[4]  Carlos Galup-Montoro,et al.  A 2-nW 1.1-V self-biased current reference in CMOS technology , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  H. Grubin The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[6]  Xing Zhou,et al.  Compact Zero-Temperature Coefficient Modeling Approach for MOSFETs Based on Unified Regional Modeling of Surface Potential , 2013, IEEE Transactions on Electron Devices.

[7]  Carlos Galup-Montoro,et al.  CMOS Analog Design Using All-Region MOSFET Modeling by Márcio Cherem Schneider , 2010 .

[8]  Paul Ampadu,et al.  Managing Temperature Effects in Nanoscale Adaptive Systems , 2011 .

[9]  S. Sze,et al.  Physics of Semiconductor Devices: Sze/Physics , 2006 .

[10]  Abdelhalim Bendali,et al.  A 1-V CMOS Current Reference With Temperature and Process Compensation , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  I. Filanovsky,et al.  Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits , 2001 .

[12]  M. El Kaamouchi,et al.  Zero-Temperature-Coefficient biasing point of 2.4-GHz LNA in PD SOI CMOS technology , 2007, 2007 European Microwave Integrated Circuit Conference.