Design of a low-power quadrature LC-VCO in 65 nm CMOS

This paper presents the design of a low-power quadrature oscillator for frequency synthesis in intermediate frequency over fiber (IFoF) applications at the lower-end of the 5G WiFi band. It is formed by two class-B LC-VCOs connected in a cross-coupled configuration. A cascaded architecture has been used for the coupling stages in order to stabilize the oscillation by minimizing bimodal oscillation and the back coupling between the two coupled LC-VCO stages. The prototype has been designed in a standard 65 nm process fed at 0.9 V instead of the nominal 1.2 V. It achieves a tuning range from 4.9GHz to 5.75 GHz, and a phase noise figure of −110.5 dBc/Hz at 1 MHz from the carrier at the maximum oscillating frequency of 5.75 GHz, for which the oscillation amplitude is close to 300 mV. Excluding the output buffer implemented for testing, the proposed quadrature oscillator consumes only 1.8mW, which yields a FoM of 182.7dB.