Exact and Approximate Methods of Switching Activity Estimation in Sequential Logic Circuits

Recently developed methods for power estimation have primarily focused on combinational logic. In this paper, we present a framework for the e cient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate, average switching activity estimation for sequential circuits is considerably more di cult than for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to accurately estimate the power dissipation of sequential circuits by computing the exact state probabilities in steady state. However, the Chapman-Kolmogorov method requires the solution of a linear system of equations of size 2 N , where N is the number of ipops in the machine. We describe a comprehensive framework for exact and approximate switching activity estimation in this paper. The basic computation step is the solution of a non-linear system of equations. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1 3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have signi cantly greater inaccuracies. J. Monteiro and S. Devadas were supported in part by the Defense Advanced Research Projects Agency under contract N00014-91-J-1698 and in part by a NSF Young Investigator Award with matching funds from Mitsubishi and IBM Corporation. C-Y. Tsui, M. Pedram and A. Despain are with the Department of Electrical Engineering at the University of Southern California. J. Monteiro and S. Devadas are with the Department of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology, Cambridge. B. Lin is with IMEC, Belgium. Latches Combinational Logic P r i m a r y I n p u t s P r i m a r y O u t p u t s Present States Next States Clock Figure 1: A Synchronous Sequential Circuit