POSTER: Fault-tolerant execution on COTS multi-core processors with hardware transactional memory support
暂无分享,去创建一个
Theo Ungerer | Gilles Pokam | Youfeng Wu | Florian Haas | Sebastian Weis | Gilles A. Pokam | Youfeng Wu | T. Ungerer | Florian Haas | Sebastian Weis
[1] Osman S. Unsal,et al. Fault tolerance for multi-threaded applications by leveraging hardware transactional memory , 2013, CF '13.
[2] Shubu Mukherjee,et al. Architecture Design for Soft Errors , 2008 .
[3] John L. Henning. SPEC CPU2006 benchmark descriptions , 2006, CARN.
[4] Stéphan Jourdan,et al. Haswell: The Fourth-Generation Intel Core Processor , 2014, IEEE Micro.
[5] Babak Falsafi,et al. Reunion: Complexity-Effective Multicore Redundancy , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).
[6] Christof Fetzer,et al. Transactional memory for dependable embedded systems , 2011, 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops (DSN-W).
[7] Shubhendu S. Mukherjee,et al. Transient fault detection via simultaneous multithreading , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).
[8] Theo Ungerer,et al. Exploiting Intel TSX for fault-tolerant execution in safety-critical systems , 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).
[9] David I. August,et al. SWIFT: software implemented fault tolerance , 2005, International Symposium on Code Generation and Optimization.
[10] Michael Laurenzano,et al. PEBIL: Efficient static binary instrumentation for Linux , 2010, 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS).
[11] Theo Ungerer,et al. Fault-Tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support , 2017, ARCS.
[12] Tipp Moseley,et al. PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures , 2009, IEEE Transactions on Dependable and Secure Computing.
[13] Christof Fetzer,et al. HAFT: hardware-assisted fault tolerance , 2016, EuroSys.
[14] Engin Ipek,et al. Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor , 2007, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07).
[15] Maurice Herlihy,et al. Transactional Memory: Architectural Support For Lock-free Data Structures , 1993, Proceedings of the 20th Annual International Symposium on Computer Architecture.