Design of Testable Structures Defined by Simple Loops
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[1] William H. Kautz. Testing for Faults in Combinational Cellular Logic Arrays , 1967, SWAT.
[2] Harold S. Stone,et al. Parallel Processing with the Perfect Shuffle , 1971, IEEE Transactions on Computers.
[3] William A. Johnson,et al. Mixed-level simulation from a hierarchical CHDL , 1980, SIGD.
[4] Yaohan Chu,et al. Computer organization and microprogramming , 1972 .
[5] Francisco J. O. Dias,et al. Truth-Table Verification of an Iterative Logic Array , 1976, IEEE Transactions on Computers.
[6] David A. Huffman,et al. Testing for Faults in Cellular Logic Arrays , 1972 .
[7] Dwight D. Hill,et al. SABLE: A Tool for Generating Structured, Multi-Level Simulations , 1979, 16th Design Automation Conference.