N-Channel (110)-Sidewall Strained FinFETs With Silicon–Carbon Source and Drain Stressors and Tensile Capping Layer
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Yee-Chia Yeo | Tsung-Yang Liow | N. Balasubramanian | Chih-Hang Tung | Y. Yeo | G. Samudra | N. Balasubramanian | K. Tan | T. Liow | C. Tung | G.S. Samudra | Kian-Ming Tan | R.T.-P. Lee | R.T.P. Lee
[1] C. Hu,et al. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .
[2] Jeffrey Bokor,et al. Extremely scaled silicon nano-CMOS devices , 2003, Proc. IEEE.
[3] G. Dewey,et al. Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
[4] E. Sleeckx,et al. Performance improvement of tall triple gate devices with strained SiN layers , 2005, IEEE Electron Device Letters.
[5] Charles S. Smith. Piezoresistance Effect in Germanium and Silicon , 1954 .
[6] Yasuhiko Ishikawa,et al. Thermal agglomeration of single-crystalline Si layer on buried SiO2 in ultrahigh vacuum , 2002 .
[7] Yee-Chia Yeo,et al. Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions , 2006, 2006 International SiGe Technology and Device Meeting.
[8] B. Ghyselen,et al. Performance Enhancement of MUGFET Devices Using Super Critical Strained-SOI (SC-SSOI) and CESL , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
[9] M. Tabe,et al. Effect of patterning on thermal agglomeration of ultrathin silicon-on-insulator layer , 2002 .
[10] M. Saitoh,et al. Carrier Transport in (110) nMOSFETs: Subband Structures, Non-Parabolicity, Mobility Characteristics, and Uniaxial Stress Engineering , 2006, 2006 International Electron Devices Meeting.
[11] Chenming Hu,et al. 5nm-gate nanowire FinFET , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
[12] Yee-Chia Yeo,et al. Strained N-Channel FinFETs with 25 nm Gate Length and Silicon-Carbon Source/Drain Regions for Performance Enhancement , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
[13] Yasuhiko Ishikawa,et al. Pattern-induced alignment of silicon islands on buried oxide layer of silicon-on-insulator structure , 2003 .
[14] Bin Yu,et al. FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.
[15] C. Mazure,et al. Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility , 2006, IEEE Electron Device Letters.
[16] Zheng Guo,et al. FinFET-based SRAM design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..
[17] Ying Zhang,et al. Extension and source/drain design for high-performance FinFET devices , 2003 .
[18] Y. Kanda,et al. A graphical representation of the piezoresistance coefficients in silicon , 1982, IEEE Transactions on Electron Devices.
[19] T. Tezuka,et al. Electron Transport Properties of Ultrathin-body and Tri-gate SOI nMOSFETs with Biaxial and Uniaxial Strain , 2006, 2006 International Electron Devices Meeting.
[20] Chi On Chui,et al. Dual stress capping layer enhancement study for hybrid orientation finFET CMOS technology , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..