SRAM HTOL Vccmin shift analysis for process control

Static Random Access Memory (SRAM) is a preferable test vehicle even when semiconductor technology scales down to 28nm node. To tolerate aging induced SRAM device degradation, a higher Vccmin window at Time Zero (T0) is needed to ensure SRAM HTOL (High Temperature of Lift Time) reliability performance. However, Vccmin shift outlier is often observed post HTOL stress, which cannot be explained as device BTI degradation only based on the Vccmin main distribution. Our work provides a correlation study between package level SRAM HTOL Vccmin shift and process controlling & process reliability evaluation. Based on the correlation, it is possible to predict the production failure rate and the failure mechanism. SRAM HTOL Vccmin shift failure follows a normal distribution, which is defined as a function of dimension variation. The study shows that the poly gate and CT (Contact) integration is one of the factors to affect HTOL early failure. Moreover, gate oxide integration (GOI) test result at process reliability phase can also reflect the HTOL Vccmin shift, which is related with Ni-piping and SiGe junction events.