A 3.75Gbps Configurable Continuous Time Linear Equalizer and 3-tap Decision Feedback Equalizer in 65nm CMOS

Abstract. This paper describes the design of the architecture and circuit block of the RX receiver’s equalizer, which is used to reduce the inter-symbol-interference(ISI) in high-speed transmission backplane, and a 3,75Gbps configurable Continuous Time Linear Equalizer (CTLE) and 3-tap configurable Decision Feedback Equalizer (DFE) are designed and implemented in 65nm CMOS Technology. Those equalizer can be configured according to different channel conditions and the equalizer provides continuous operation range between 0.5Gbps-3.75Gbps, which are designed to work together to mitigate some or most of hte insertion loss and help the receiver to scale and optimize across different needs and applization. The simulation result shows that the horizontal eye opening of recovered data is 0.75UI at 3.75Gbps and the high frequency boost is up to 11dB.

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