Hotspots Elimination and Temperature Flattening in VLSI Circuits

This paper proposes a new solution to the problem of eliminating hotspots from gate-level netlists as well as examines the effects of timing constraints on the temperature reduction and the overall temperature flattening on the chip. Our core technique consists of three steps. First, a thermal analysis is carried out for logic netlists. (The netlists are assumed to be either isolated or embedded in a larger system with macro-cells.) We then apply a new technique, called isothermal logic partitioning technique ( LP-temp), to the netlists, which essentially builds isothermal logic clusters for the netlists and splits each of the logic clusters exceeding the maximum allowed temperature through its hottest point. This will enlarge a contact point for the hotspot to cool down. Finally, the entire system is replaced using a custom designed temperature-aware floorplanner so that the temperature across the entire system is reduced and flattened. We have developed a thermal-aware design flow, integrating our thermal-aware logic partitioning technique with a timing and thermal-aware floorplanner. Two cases were analyzed: (tight timing) LP-temp combined with the timing and thermal-aware floorplanner, where the partitioned units by LP-temp are replaced locally considering a tight timing budget (5% timing degradation); (loose timing) LP-temp combined with thermal-aware replacement, considering a loose timing budget (10% timing degradation). From experimentations using a set of benchmark designs, it is confirmed that our temperature reduction technique is effective, generating designs with an average of 5.54% and 9.9% more reduction of peak temperature (on average) for the cases of tight and loose timing than that of the designs by a conventional thermal-aware floorplanner without using LP-temp, respectively. We also analyzed the effect of our proposed technique on field-programmable gate arrays (FPGAs) in order to contrast its effectiveness on systems with hotspots on hardmacros. Results show that our technique can reduce the temperature in these systems on average 3.40% and 6.61% for the case of loose and tight timing constraints respectively compared to the thermal-aware floorplanner without using LP-temp .

[1]  Taewhan Kim,et al.  Temperature-Aware Compilation for VLIWProcessors , 2007, 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007).

[2]  Stephen H. Gunther,et al.  Managing the Impact of Increasing Microprocessor Power Consumption , 2001 .

[3]  Jan M. Van Campenhout,et al.  Generating new benchmark designs using a multi-terminal net model , 1999, Integr..

[4]  R. Otten.  Automatic Floorplan Design , 1982, DAC 1982.

[5]  Timothy S. Fisher,et al.  Transient thermal management of portable electronics using heat storage and dynamic power dissipation control , 1998 .

[6]  Resve Saleh,et al.  Analysis and Design of Digital Integrated Circuits , 1983 .

[7]  Seung-Moon Yoo,et al.  A framework for dynamic energy efficiency and temperature management , 2000, Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000.

[8]  Massoud Pedram,et al.  Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits , 2005, IEICE Trans. Electron..

[9]  Nikil D. Dutt,et al.  Floorplan driven leakage power aware IP-based SoC design space exploration , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[10]  Kevin Skadron,et al.  Compact thermal modeling for temperature-aware design , 2004, Proceedings. 41st Design Automation Conference, 2004..

[11]  Sung-Mo Kang,et al.  Standard cell placement for even on-chip thermal distribution , 1999, ISPD '99.

[12]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[13]  K. Banerjee,et al.  Global (interconnect) warming , 2001 .

[14]  Margaret Martonosi,et al.  Dynamic thermal management for high-performance microprocessors , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[15]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[16]  Y. Çengel.  Introduction to thermodynamics and heat transfer , 1996 .

[17]  Benjamin Carrión Schäfer,et al.  Thermal-Aware Instruction Assignment for VLIW Processors 1 , 2007 .

[18]  C. L. Liu,et al.  A New Algorithm for Floorplan Design , 1986, DAC 1986.

[19]  Martin D. F. Wong,et al.  A matrix synthesis approach to thermal placement , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  T. Ohtsuki,et al.  Recent advances in VLSI layout , 1990, Proc. IEEE.

[22]  Nobuto Ono,et al.  On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design , 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[23]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Seda Ogrenci Memik,et al.  Temperature-aware resource allocation and binding in high-level synthesis , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[25]  D. A. Mooney,et al.  Introduction to Thermodynamics and Heat Transfer , 1956 .

[26]  Kaustav Banerjee,et al.  Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[27]  S. Naffziger,et al.  A 90-nm variable frequency clock system for a power-managed itanium architecture processor , 2006, IEEE Journal of Solid-State Circuits.