Experimental Investigations on Carrier Transport in Si Nanowire Transistors: Ballistic Efficiency and Apparent Mobility

As devices continue scaling down into nanometer regime, carrier transport becomes critically important. In this paper, experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is adopted, which takes into account the impact of temperature dependence of parasitic source resistance in SNWTs. The highest ballistic efficiency at room temperature is observed in sub-40-nm n-channel SNWTs due to their quasi-1-D carrier transport. The apparent mobility of GAA SNWTs are also extracted, showing their close proximity to the ballistic limit as shrinking the gate length, which can be explained by Shur's model. The physical understanding of the apparent mobility in SNWTs is also discussed using flux's scattering matrix method.

[1]  Charles M. Lieber,et al.  Coaxial silicon nanowires as solar cells and nanoelectronic power sources , 2007, Nature.

[2]  G. Ghibaudo,et al.  Electron mobility in quasi-ballistic Si MOSFETs , 2006 .

[3]  M. Lundstrom,et al.  Essential physics of carrier transport in nanoscale MOSFETs , 2002 .

[4]  Chenming Hu,et al.  5nm-gate nanowire FinFET , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[5]  Shinichi Tanaka,et al.  On the Carrier Mobility in Forward-Biased Semiconductor Barriers. , 1995 .

[6]  B. Ryu,et al.  Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires , 2006, 2006 International Electron Devices Meeting.

[7]  E. Polizzi,et al.  A computational study of ballistic silicon nanowire transistors , 2003, IEEE International Electron Devices Meeting 2003.

[8]  M. Shur,et al.  Low ballistic mobility in submicron HEMTs , 2002, IEEE Electron Device Letters.

[9]  Charles M. Lieber,et al.  High Performance Silicon Nanowire Field Effect Transistors , 2003 .

[10]  Yee-Chia Yeo,et al.  Carrier Transport Characteristics of Sub-30 nm Strained N-Channel FinFETs Featuring Silicon-Carbon Source/Drain Regions and Methods for Further Performance Enhancement , 2006, 2006 International Electron Devices Meeting.

[11]  R. L. Longini,et al.  Alternative Approach to the Solution of Added Carrier Transport Problems in Semiconductors , 1961 .

[12]  D. Frank,et al.  25 nm CMOS design considerations , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[13]  Horng-Chih Lin,et al.  The impact of uniaxial strain engineering on channel backscattering in nanoscale MOSFETs , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[14]  Mark S. Lundstrom,et al.  Nanoscale Transistors: Device Physics, Modeling and Simulation , 2005 .

[15]  Gerard Ghibaudo,et al.  Characterization of the effective mobility by split C(V) technique in sub 0.1 μm Si and SiGe PMOSFETs , 2005 .

[16]  K. Natori.  Ballistic metal-oxide-semiconductor field effect transistor , 1994 .

[17]  G. Ghibaudo,et al.  Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling , 2006, 2006 International Electron Devices Meeting.

[18]  G. Le Carval,et al.  Experimental determination of the channel backscattering coefficient on 10–70 nm-metal-gate Double-Gate transistors , 2007 .

[19]  M. Lundstrom.  On the mobility versus drain current relation for a nanoscale MOSFET , 2001, IEEE Electron Device Letters.

[20]  D. Schroder.  Semiconductor Material and Device Characterization , 1990 .

[21]  D. Schroder.  Semiconductor Material and Device Characterization, 3rd Edition , 2005 .

[22]  Mark S. Lundstrom.  Elementary scattering theory of the Si MOSFET , 1997, IEEE Electron Device Letters.

[23]  Electron-phonon scattering in quantum point contacts. , 2002, Physical review letters.

[24]  B. Ryu,et al.  Observation of Single Electron Tunneling and Ballistic Transport in Twin Silicon Nanowire MOSFETs (TSNWFETs) Fabricated by Top-Down CMOS Process , 2006, 2006 International Electron Devices Meeting.

[25]  Candace K. Chan,et al.  High-performance lithium battery anodes using silicon nanowires. , 2008, Nature nanotechnology.

[26]  A. Bournel,et al.  Monte Carlo study of apparent mobility reduction in nano-MOSFETs , 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

[27]  G. Gildenblat,et al.  One-flux theory of a nonabsorbing barrier , 2002 .

[28]  Mark Lundstrom,et al.  Drift-diffusion equation for ballistic transport in nanoscale metal-oxide-semiconductor field effect transistors , 2002 .

[29]  Chih-Sheng Chang,et al.  Temperature dependent channel backscattering coefficients in nanoscale MOSFETs , 2002, Digest. International Electron Devices Meeting,.

[30]  M.A. Alam,et al.  Design Considerations of Silicon Nanowire Biosensors , 2007, IEEE Transactions on Electron Devices.

[31]  A. Majumdar,et al.  Enhanced Thermoelectric Performance of Rough Silicon Nanowires. , 2008 .

[32]  Ru Huang,et al.  New Self-Aligned Silicon Nanowire Transistors on Bulk Substrate Fabricated by Epi-Free Compatible CMOS Technology: Process Integration, Experimental Characterization of Carrier Transport and Low Frequency noise , 2007, 2007 IEEE International Electron Devices Meeting.

[33]  M. Vinet,et al.  Experimental Comparison Between Sub-0.1-$\mu{\hbox{m}}$ Ultrathin SOI Single- and Double-Gate MOSFETs: Performance and Mobility , 2006, IEEE Transactions on Nanotechnology.

[34]  Peidong Yang,et al.  Silicon Vertically Integrated Nanowire Field Effect Transistors , 2006 .

[35]  B. Ryu,et al.  High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[36]  Gerard Ghibaudo,et al.  New method for the extraction of MOSFET parameters , 1988 .

[37]  S.C. Rustagi,et al.  High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices , 2006, IEEE Electron Device Letters.