A 40 Mb/s soft-output Viterbi decoder

Soft-output decoding has evolved as a key technology for new error correction approaches with unprecedented performance as well as for improvement of well established transmission techniques. In this paper, we present a high-speed VLSI implementation of the soft-output Viterbi algorithm, a low complexity soft-output algorithm, for a 16-state convolutional code. The 43 mm/sup 2/ standard cell chip achieves a simulated throughput of 40 Mb/s, while tested samples achieved a throughput of 50 Mb/s. The chip is roughly twice as big as a 16-state Viterbi decoder without soft outputs. It is thus shown with the design that transmission schemes using soft-output decoding can be considered practical even at very high throughput. Since such decoding systems are more complex to design than hard output systems, special emphasis is placed on the employed design methodology. >

[1]  Heinrich Meyr,et al.  High-speed VLSI architectures for soft-output viterbi decoding , 1994, J. VLSI Signal Process..

[2]  E. Offer,et al.  Improving the standard coding system for deep space missions , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[3]  H. Meyr,et al.  Soft-output Viterbi decoding: VLSI implementation issues , 1993, IEEE 43rd Vehicular Technology Conference.

[4]  Carl-Erik W. Sundberg,et al.  Advanced techniques for modulation, error correction, channel equalization, and diversity , 1993, AT&T Technical Journal.

[5]  John Cocke,et al.  Optimal decoding of linear codes for minimizing symbol error rate (Corresp.) , 1974, IEEE Trans. Inf. Theory.

[6]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[7]  Peter Adam Hoeher,et al.  Separable MAP "filters" for the decoding of product and concatenated codes , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[8]  Peter Adam Hoeher.  TCM on frequency-selective fading channels: a comparison of soft-output probabilistic equalizers , 1990, [Proceedings] GLOBECOM '90: IEEE Global Telecommunications Conference and Exhibition.

[9]  H. Meyr,et al.  Map channel decoding: Algorithm and VLSI architecture , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.

[10]  M. Nasiri-Kenari,et al.  Matched spectral-null codes with soft-decision outputs , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[11]  Claude Berrou,et al.  A low complexity soft-output Viterbi decoder architecture , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[12]  Heinrich Meyr,et al.  A new postprocessing architecture for soft output Viterbi decoding , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

[13]  Jr. G. Forney,et al.  The viterbi algorithm , 1973 .

[14]  Erik Paaske.  Improved decoding for a concatenated coding system recommended by CCSDS , 1990, IEEE Trans. Commun..

[15]  Jens Sparsø,et al.  An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures , 1991 .

[16]  Peter Adam Hoeher.  Advances in soft-output decoding , 1993, Proceedings of GLOBECOM '93. IEEE Global Telecommunications Conference.

[17]  H. Meyr,et al.  Systematic design optimization of a competitive soft-concatenated decoding system , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.

[18]  Shuji Kubota,et al.  DSD (Double Soft Decision) Concatenated FEC Scheme in Mobile Satellite Communication Systems , 1992, IEEE J. Sel. Areas Commun..

[19]  R. A. Harris,et al.  Low complexity concatenated coding schemes for digital satellite communications , 1989 .