Multiport register file memory cell

The invention specifically relates to a multiport register file memory cell, which belongs to the technical field of integrated circuits. The memory cell is composed of 8 NMOS transistors and 2 PMOS transistors, wherein 4 NMOS transistors and the 2 PMOS transistors compose a coupled inverter which is used for storing data, and the rest 4 NMOS transistors are read-write transistors. The locating and wiring manner of the memory cell is as follows: there is a layout with an N well, a polysilicon layer, an active region layer, CT and M1 corresponding to the register file memory cell; the register file memory cell has a longitudinally and bilaterally symmetric structure. The six transistors of the coupled inverter employ two polysilicon gates, so asymmetry of the transistors caused by manufacture deviation is greatly reduced, and noise margin is broadened; the two PMOS transistors use a drain terminal active region together, the 4 NMOS transistors and the 4 read-write transistors use a source terminal active region together, so the number of through holes is decreased and the area of the cell is greatly reduced.