Graph algorithms for clock schedule optimization

Performance driven synthesis of sequential circuits relies on techniquessuch as optimal clocking, retiming and resynthesis. In this paper we address the optimal clockingproblem and demonstrate that it is reducible to a parametric shortest path problem. We use constraints that take into account both the short and long paths. The main contributions are efjicient graph algorithms to solve the set of constraints necessary for correct clocking.

[1]  Alberto L. Sangiovanni-Vincentelli,et al.  Timing Analysis in a Logic Synthesis Environment , 1989, 26th ACM/IEEE Design Automation Conference.

[2]  Robert K. Brayton,et al.  Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[3]  Stephen H. Unger,et al.  Clocking Schemes for High-Speed Digital Systems , 1986, IEEE Transactions on Computers.

[4]  John K. Ousterhout.  A Switch-Level Timing Verifier for Digital MOS VLSI , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Carlo H. Séquin,et al.  ATV: an abstract timing verifier , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[6]  R. K. Brayton,et al.  Graph algorithms for clock schedule optimization , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[7]  Nicholas C. Rumin,et al.  Automatic determination of optimal clocking parameters in synchronous MOS VLSI circuits , 1988 .

[8]  Robert B. Hitchcock,et al.  Timing verification and the timing analysis program , 1988, DAC 1982.

[9]  Trevor N. Mudge,et al.  CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[10]  Thomas G. Szymanski,et al.  Computing optimal clock schedules , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.