Predicting processor performance with a machine learnt model
暂无分享,去创建一个
[1] Daniel J. Pease,et al. A mathematical model of trace cache , 2002, Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors.
[2] Thomas G. Dietterich. What is machine learning? , 2020, Archives of Disease in Childhood.
[3] Thomas F. Wenisch,et al. SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling , 2003, ISCA '03.
[4] G. G. Stokes. "J." , 1890, The New Yale Book of Quotations.
[5] James E. Smith,et al. Comparing program phase detection techniques , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..
[6] Greg Hamerly,et al. SimPoint 3.0: Faster and More Flexible Program Analysis , 2005 .
[7] John Paul Shen,et al. Theoretical modeling of superscalar processor performance , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.
[8] Brad Calder,et al. SimPoint 3.0: Faster and More Flexible Program Phase Analysis , 2005, J. Instr. Level Parallelism.
[9] Kapil Vaswani,et al. A Predictive Performance Model for Superscalar Processors , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).
[10] Nader Bagherzadeh,et al. Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors , 1998, IEEE Trans. Parallel Distributed Syst..