Understanding PBTI in Replacement Metal Gate Ge n-Channel FETs With Ultrathin Al2O3 and GeOx ILs Using Ultrafast Charge Trap–Detrap Techniques

We report positive bias temperature instability data in replacement metal gate Ge n-channel metal–oxide–semiconductor field-effect transistors with an <italic>in-situ</italic> gate stack employing an ultrathin (5 Å), stable Al<sub>2</sub>O<sub>3</sub> interlayer (IL) using ultrafast (~microseconds) characterization techniques that ensure recovery artifact-free measurements. Comparison with state-of-the-art GeO<sub><italic>x</italic></sub> IL is also reported besides establishing correlations between band-edge interface trap density (<inline-formula> <tex-math notation="LaTeX">${D}_{\text {it}}$ </tex-math></inline-formula>), mobility (<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula>), and threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula>) instability. Ultrafast measure-stress-measure (UF-MSM), ultrafast measure-stress-detrap-measure (UF-MSDM), stress-induced-leakage-current (SILC), direct-current current–voltage (DCIV), split capacitance–voltage (<inline-formula> <tex-math notation="LaTeX">${C}$ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula>), and low-temperature full conductance techniques along with a compact model demonstrate that: 1) trap generation occurs at IL/high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> interface during stress; 2) an increase in <inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula> with reduction in <inline-formula> <tex-math notation="LaTeX">${D}_{\text {it}}$ </tex-math></inline-formula> does not guarantee better reliability, i.e., <inline-formula> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> shift and <inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula> are uncorrelated due to their dependence on separate regions of the gate stack; 3) contributions to total <inline-formula> <tex-math notation="LaTeX">${V}_{\text {T}}$ </tex-math></inline-formula> degradation from trapping and generated traps are mutually exclusive; 4) UF-MSDM is a powerful tool to estimate trap generation; and 5) <inline-formula> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> degradation is directly proportional to high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> thickness, varies inversely with IL thickness, and reduces with annealing.

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