CMOS Transconductors With Continuous Tuning Using FGMOS Balanced Output Current Scaling

A technique to achieve highly linear scaling of differential currents in CMOS technology is presented. It is based on operation in weak or moderate inversion, and features performance improvements over previous proposals aimed to the same goal, like reduced supply voltage requirements, increased power efficiency, and avoidance of bulk effect. As an example, this technique is applied to attain continuous tuning for two novel voltage-to-current converters, achieving highly linear programmable transconductance over a rail-to-rail input range. Both implementations fabricated in a 0.5-mum CMOS technology using a dual supply of plusmn1.5 V achieve a THD of -60 dB with differential input swings of 6 Vpp (i.e., twice the supply voltage). The area and power consumption are 0.12 mm2 and 2.6 mW for the first implementation and 0.11 mm2 and 2.2 mW for the second one, respectively.

[1]  Esther Rodriguez-Villegas,et al.  Solution to trapped charge in FGMOS transistors , 2003 .

[2]  K. Smith,et al.  A second-generation current conveyor and its applications , 1970, IEEE Transactions on Circuit Theory.

[3]  W. Guggenbuhl,et al.  An analog trimming circuit based on a floating-gate device , 1988 .

[4]  A.H.M. van Roermund,et al.  A CMOS V-I converter with 75-dB SFDR and 360-/spl mu/W power consumption , 2005, IEEE Journal of Solid-State Circuits.

[5]  A.J. Lopez-Martin,et al.  A CMOS transconductor with multidecade tuning using balanced current scaling in moderate inversion , 2005, IEEE Journal of Solid-State Circuits.

[6]  Jaime Ramirez-Angulo,et al.  Low-voltage circuits building blocks using multiple-input floating-gate transistors , 1995 .

[7]  Jaime Ramirez-Angulo,et al.  MITE circuits: the continuous-time counterpart to switched-capacitor circuits , 2001 .

[8]  Edgar Sánchez-Sinencio,et al.  Robust highly linear high-frequency CMOS OTA with IM3 below - 70 dB at 26 MHz , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Y. Tsividis.  Operation and modeling of the MOS transistor , 1987 .

[10]  Barrie Gilbert,et al.  Translinear circuits: An historical overview , 1996 .

[11]  Ko-chi Kuo,et al.  A linear MOS transconductor using source degeneration and adaptive biasing , 2001 .

[12]  Bing J. Sheu,et al.  Analog floating-gate synapses for general-purpose VLSI neural computation , 1991 .

[13]  E. Sanchez-Sinencio,et al.  Active filter design using operational transconductance amplifiers: A tutorial , 1985, IEEE Circuits and Devices Magazine.

[14]  H. Hegt,et al.  CMOS V-I converter with 75dB SFDR and 360/spl mu/W power consumption , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[15]  M. Tarsia,et al.  Design considerations and implementation of a programmable high-frequency continuous-time filter and variable-gain amplifier in submicrometer CMOS , 1999, IEEE J. Solid State Circuits.

[16]  Didier Rene Haspeslagh,et al.  A highly linear CMOS G/sub m/-C bandpass filter with on-chip frequency tuning , 1997 .

[17]  Terri S. Fiez,et al.  A CMOS transconductor with 80-dB SFDR up to 10 MHz , 2002 .

[18]  Saska Lindfors,et al.  A 3-V continuous-time filter with on-chip tuning for IS-95 , 1999 .

[19]  E. Seevinck,et al.  CMOS translinear circuits for minimum supply voltage , 2000 .

[20]  Bram Nauta,et al.  A CMOS "soft-switched" transconductor and its application in gain control and filters , 1997 .

[21]  E.K.F. Lee.  Low-voltage op amp design and differential difference amplifier design using linear transconductor with resistor input , 2000 .

[22]  K. W. Martin,et al.  A BiCMOS low-distortion 8-MHz low-pass filter , 1993 .

[23]  K. Vavelidis,et al.  Simple 'reconciliation' MOSFET model valid in all regions , 1995 .

[24]  José Silva-Martínez,et al.  A 30-MHz Fifth-Order Elliptic Low-Pass CMOS Filter With 65-dB Spurious-Free Dynamic Range , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[25]  Terri S. Fiez,et al.  Analog VLSI : signal and information processing , 1994 .

[26]  G. A. Rigby,et al.  A 1-V CMOS D/A converter with multi-input floating-gate MOSFET , 1999, IEEE J. Solid State Circuits.

[27]  José Silva-Martínez,et al.  OTA linearity enhancement technique for high frequency applications with IM3 below -65 dB , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[28]  D. J. Allstot,et al.  Low-power CMOS continuous-time filters , 1996 .

[29]  Ramón González Carvajal,et al.  Highly linear programmable balanced current scaling technique in moderate inversion , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[30]  Edgar Sánchez-Sinencio,et al.  Frequency-dependent harmonic-distortion analysis of a linearized cross-coupled CMOS OTA and its application to OTA-C filters , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[31]  Tadashi Shibata,et al.  A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .

[32]  Edgar Sanchez-Sinencio,et al.  CMOS transconductance amplifiers, architectures and active filters: a tutorial , 2000 .