Restrict Encoding for Mixed-Mode BIST

Programmable mixed-mode BIST schemes combine pseudo-random pattern testing and deterministic test. This paper presents a synthesis technique for a mixed-mode BIST scheme which is able to exploit the regularities of a deterministic test pattern set for minimizing the hardware overhead and memory requirements. The scheme saves more than 50% hardware costs compared with the best schemes known so far while complete programmability is still preserved.

[1]  Janak H. Patel,et al.  Test set compaction algorithms for combinational circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[2]  Subhasish Mitra,et al.  Efficient Seed Utilization for Reseeding based Compression , 2003 .

[3]  Arthur D. Friedman,et al.  Test Point Placement to Simplify Fault Detection , 1974, IEEE Transactions on Computers.

[4]  Nur A. Touba,et al.  Relating entropy theory to test data compression , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[5]  Nur A. Touba,et al.  Altering a pseudo-random bit sequence for scan-based BIST , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[6]  Hans-Joachim Wunderlich,et al.  BIST for systems-on-a-chip , 1998, Integr..

[7]  Hans-Joachim Wunderlich,et al.  Combining deterministic logic BIST with test point insertion , 2002, Proceedings The Seventh IEEE European Test Workshop.

[8]  Wenjing Rao,et al.  Test application time and volume compression through seed overlapping , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[9]  Ad J. van de Goor,et al.  Test point insertion for compact test sets , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[10]  Mark Mohammad Tehranipoor,et al.  Nine-coded compression technique for testing embedded cores in SoCs , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Nur A. Touba,et al.  Test vector encoding using partial LFSR reseeding , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[12]  Friedrich Hapke,et al.  Efficient pattern mapping for deterministic logic BIST , 2004, 2004 International Conferce on Test.

[13]  Nur A. Touba,et al.  Test data compression using dictionaries with selective entries and fixed-length indices , 2003, TODE.

[14]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[15]  Bernard Courtois,et al.  Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers , 1995, IEEE Trans. Computers.

[16]  Sybille Hellebrand,et al.  Data compression for multiple scan chains using dictionaries with corrections , 2004 .

[17]  Ahmad A. Al-Yamani,et al.  BIST reseeding with very few seeds , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[18]  B. Koneman,et al.  LFSR-Coded Test Patterns for Scan Designs , 1993 .

[19]  Friedrich Hapke,et al.  Programmable deterministic Built-In Self-Test , 2007, 2007 IEEE International Test Conference.

[20]  Janusz Rajski,et al.  Test Data Decompression for Multiple Scan Designs with Boundary Scan , 1998, IEEE Trans. Computers.

[21]  Irith Pomeranz,et al.  On static test compaction and test pattern ordering for scan designs , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[22]  Ajay Khoche,et al.  Packet-based input test data compression techniques , 2002, Proceedings. International Test Conference.

[23]  Nur A. Touba,et al.  3-stage variable length continuous-flow scan vector decompression scheme , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[24]  Irith Pomeranz,et al.  On compacting test sets by addition and removal of test vectors , 1994, Proceedings of IEEE VLSI Test Symposium.

[25]  Sudhakar M. Reddy,et al.  Improved algorithms for constructive multi-phase test point insertion for scan based BIST , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[26]  H. Wunderlich,et al.  Bit-flipping BIST , 1996, ICCAD 1996.

[27]  Brion L. Keller,et al.  A SmartBIST variant with guaranteed encoding , 2001, Proceedings 10th Asian Test Symposium.