论文信息 - Low power design of two-dimensional DCT

Low power design of two-dimensional DCT

This paper discusses several techniques used in reducing power for a two-dimensional discrete cosine transform (2D DCT) design. These techniques include removal of circuit blocks that computes the DCT coefficients which will be quantized to zeros, re-ordering of operations in constant-multipliers to reduce transition probability, and re-designing cells for low-voltage operation. An 8/spl times/8 2D DCT built with two 1D DCT employing these techniques is designed. The estimated power consumption for this 8/spl times/8 2D DCT is 16.95 mW.

Shih-Lien Lu | J. Li

[1] Jhing-Fa Wang,et al. A high throughput-rate architecture for 8*8 2D DCT , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[2] Joos Vandewalle,et al. Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators , 1993 .

[3] Gregory K. Wallace,et al. The JPEG still picture compression standard , 1992 .

[4] Alan N. Willson,et al. A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications , 1995, IEEE Trans. Circuits Syst. Video Technol..

[5] Lee-Sup Kim,et al. 200 MHz video compression macrocells using low-swing differential logic , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[6] K. J. Ray Liu,et al. A low-power and low-complexity DCT/IDCT VLSI architecture based on backward Chebyshev recursion , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[7] Jan M. Rabaey,et al. Digital Integrated Circuits: A Design Perspective , 1995 .

[8] Christer Svensson,et al. Trading speed for low power by choice of supply and threshold voltages , 1993 .

[9] Thomas D. Burd. Low-Power CMOS Library Design Methodology , 1994 .

[10] Ting Chen,et al. VLSI implementation of a 16*16 discrete cosine transform , 1989 .