Towards structured ASICs using polarity-tunable Si nanowire transistors

In addition to scaling semiconductor devices down to their physical limit, novel devices show enhanced functionality compared to conventional CMOS. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., they show n- and p-type characteristics simultaneously. This phenomenon can be tamed using double-gate structures. In this paper, we present a complete framework relying on Double-Gate-all-around Vertically stacked NanoWire FETs (DG-NWFETs). Such device enables a compact realization of arithmetic logic functions and presents unprecedented interest for structured ASIC applications.

[1]  Stefan Slesazeck,et al.  Reconfigurable silicon nanowire transistors. , 2012, Nano letters.

[2]  Giovanni De Micheli,et al.  Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[3]  Yusuf Leblebici,et al.  Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors , 2012, DAC Design Automation Conference 2012.

[4]  G. Cohen,et al.  High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[5]  Giovanni De Micheli,et al.  MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

[6]  Giovanni De Micheli,et al.  Biconditional BDD: A novel canonical BDD for logic synthesis targeting XOR-rich circuits , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[7]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[8]  B. Ryu,et al.  High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[9]  C. Auth,et al.  A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[10]  Kartik Mohanram,et al.  Universal logic modules based on double-gate carbon nanotube transistors , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  Yusuf Leblebici,et al.  Vertically-stacked double-gate nanowire FETs with controllable polarity: From devices to regular ASICs , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[12]  N. Yokoyama,et al.  A polarity-controllable graphene inverter , 2010 .

[13]  Frédéric Gaffiot,et al.  CNTFET Modeling and Reconfigurable Logic-Circuit Design , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  J. Knoch,et al.  High-performance carbon nanotube field-effect transistor with tunable polarities , 2005, IEEE Transactions on Nanotechnology.

[15]  Davide Pandini,et al.  Maximization of layout printability/manufacturability by extreme layout regularity , 2007 .

[16]  Giovanni De Micheli,et al.  BDS-MAJ: A BDD-based logic synthesis tool exploiting majority logic decomposition , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[17]  E. Tutuc,et al.  Dual-gate silicon nanowire transistors with nickel silicide contacts , 2006, 2006 International Electron Devices Meeting.

[18]  G. De Micheli,et al.  Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs , 2012, 2012 International Electron Devices Meeting.