论文信息 - Four-valued memory circuit using three-peak MOS-NDR devices and circuits - 字舞流文

Four-valued memory circuit using three-peak MOS-NDR devices and circuits

A four-valued memory circuit using the three-peak MOS-NDR circuit as the driver and a current source as the load is demonstrated. The fabrication of the circuit is based on the standard 0.35 µm CMOS process.

Cher-Shiung Tsai | Yaw-Hwang Chen | Kwang-Jow Gan | L.-X. Su

[1] Kyounghoon Yang,et al. CML-type MOnostable BIstable logic element (MOBILE) using InP-based monolithic RTD/HBT technology , 2004 .

[2] Pinaki Mazumder,et al. CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices , 2001 .

[3] A. Seabaugh,et al. Nine-state resonant tunneling diode memory , 1992, IEEE Electron Device Letters.

[4] Cy Wu,et al. INTEGRATED ALPHA-TYPE DIFFERENTIAL NEGATIVE-RESISTANCE MOSFET DEVICE , 1979 .

[5] S. Sen,et al. Resonant tunneling device with multiple negative differential resistance: Digital and signal processing applications with reduced circuit complexity , 1987, IEEE Transactions on Electron Devices.

[6] Hung Chang Lin,et al. Multivalued SRAM cell using resonant tunneling diodes , 1992 .