Hot-carrier reliability assessment in CMOS digital integrated circuits

As VLSI technologies scale to deep submicron region, the DC device-based hotcarrier criterion is no longer practical for predicting hot-carrier reliability. Understanding the AC hot-carrier degradation of MOSFETs in actual circuit environment and their corresponding impact on circuit performance becomes increasingly important. The purpose of this research is to contribute to the assessment of hot-carrier reliability in digital CMOS circuits. Several critical issues that face circuit-level hot-carrier reliability evaluation are investigated, including AC hot-carrier test circuit design and characterization, AC hot-carrier degradation model calibration, the major factors determining circuit-level hot-carrier reliability, and the trade-offs between circuit-level hot-carrier lifetime underestimation and the amount of information required. In the area of experimental assessment of AC hot-carrier reliability, this thesis provides a comprehensive understanding of the key issues in designing and characterizing hot-carrier reliability test circuits. Test circuits that can provide realistic stress voltage waveforms, allow access to the internal device nodes, and provide insight about circuit performance sensitivity to hot-carrier damage are presented. New insights about previous test circuit designs are presented and additional test circuit designs are demonstrated. The design trade-offs between realistic waveform generation and internal device accessibility are analyzed and clarified. Recommendations for optimal test-circuit design for hot-carrier reliability characterization and model calibration are proposed. In the area of circuit-level hot-carrier reliability simulation, this thesis examines key issues involved in the calibration and verification of the hot-carrier degradation models that are used for AC hot-carrier reliability simulation. The need to account for the stress oxide-field dependence of the degradation model coefficients is demonstrated. The statistical confidence limits of the extracted degradation model parameters are analyzed. The sensitivity of degradation to drain and substrate current modeling errors is examined. Base on these results, the AC degradation model's statistical confidence limits are evaluated, and the accuracy and precision of AC hot-carrier reliability simulation is rigorously benchmarked against a comprehensive set of experimental AC circuit measurements. It is shown that statistical variation in the degradation model parameters has as much of an impact on the final degradation model accuracy as major changes in the circuit-design itself. In addition, knowledge about CMOS digital circuit behavior is shown to be useful in optimizing the calibration of both the degradation and SPICE model parameters. Specific recommendations are made about improving the consistency and accuracy of both degradation and SPICE model parameter extraction. Finally, the major factors that cumulatively contribute to circuit-level hot-carrier reliability are identified. The inherent inverse relationship between lifetimeunderestimation/criteria-overspecification and the amount of known device/circuit information are explored. Lifetime-underestimation/criteria-overspecification are shown to depend quite strongly on the particular "worst-case" approximations used. Each of the above concepts are illustrated using representative circuit examples and case studies. Thesis Supervisor: James E. Chung Title: Associate Professor, Electrical Engineering