Mapping arbitrary mathematical functions and dynamical systems to neuromorphic VLSI circuits for spike-based neural computation

Brain-inspired, spike-based computation in electronic systems is being investigated for developing alternative, non-conventional computing technologies. The Neural Engineering Framework provides a method for programming these devices to implement computation. In this paper we apply this approach to perform arbitrary mathematical computation using a mixed signal analog/digital neuromorphic multi-neuron VLSI chip. This is achieved by means of a network of spiking neurons with multiple weighted connections. The synaptic weights are stored in a 4-bit on-chip programmable SRAM block. We propose a parallel event-based method for calibrating appropriately the synaptic weights and demonstrate the method by encoding and decoding arbitrary mathematical functions, and by implementing dynamical systems via recurrent connections.

[1]  B. Hoefflinger.  ITRS: The International Technology Roadmap for Semiconductors , 2011 .

[2]  Andrew S. Cassidy,et al.  Design of silicon brains in the nano-CMOS era: Spiking neurons, learning synapses and neural architecture optimization , 2013, Neural Networks.

[3]  Kwabena Boahen,et al.  Silicon Neurons That Compute , 2012, ICANN.

[4]  Andrew S. Cassidy,et al.  Building block of a programmable neuromorphic substrate: A digital neurosynaptic core , 2012, The 2012 International Joint Conference on Neural Networks (IJCNN).

[5]  Chiara Bartolozzi,et al.  Synaptic Dynamics in Analog VLSI , 2007, Neural Computation.

[6]  Chris Eliasmith,et al.  Neural Engineering: Computation, Representation, and Dynamics in Neurobiological Systems , 2004, IEEE Transactions on Neural Networks.

[7]  Paul E. Hasler,et al.  Computing with networks of spiking neurons on a biophysically motivated floating-gate based neuromorphic integrated circuit , 2013, Neural Networks.

[8]  Gert Cauwenberghs,et al.  Neuromorphic Silicon Neuron Circuits , 2011, Front. Neurosci.

[9]  Paolo Lugli,et al.  Science and Engineering Beyond Moore's Law , 2012, Proceedings of the IEEE.

[10]  S. Joshi,et al.  65k-neuron integrate-and-fire array transceiver with address-event reconfigurable synaptic routing , 2012, 2012 IEEE Biomedical Circuits and Systems Conference (BioCAS).

[11]  Trevor Bekolay,et al.  A Large-Scale Model of the Functioning Brain , 2012, Science.

[12]  Giacomo Indiveri,et al.  An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory , 2014, IEEE Transactions on Biomedical Circuits and Systems.

[13]  Shi-Yu Huang,et al.  P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation , 2011, IEEE Journal of Solid-State Circuits.