A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

This paper describes an I/O scheme for use in a high-speed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to-peak jitter of 150 ps and r.m.s. jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6 /spl mu/m CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin.

[1]  Mel Bazes,et al.  A novel CMOS digital clock and data decoder , 1992 .

[2]  Keng L. Wong,et al.  A PLL clock generator with 5 to 110 MHz of lock range for microprocessors , 1992 .

[3]  Mark Horowitz,et al.  PLL design for a 500 MB/s interface , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[4]  D. Finan,et al.  FA 18.4: a phase-tolerant 3.8 GB/s data-communication router for a multiprocessor supercomputer backplane , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[5]  Thomas H. Lee,et al.  A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM , 1994, IEEE J. Solid State Circuits.

[6]  Deog-Kyoon Jeong,et al.  A Pseudo-Synchronous Skew-Insensitive I/O Scheme for High Band width Memories , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

[7]  H. Notani,et al.  A 622-MHz CMOS phase-locked loop with precharge-type phase frequency detector , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

[8]  Masashi Horiguchi,et al.  An experimental 220 MHz 1 Gb DRAM , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[9]  Deog-Kyoon Jeong,et al.  An 800 Mbps multi-channel CMOS serial link with 3/spl times/ oversampling , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.