论文信息 - Polymorphic Arrays: A Novel VLSI Layout for Systolic Computers

Polymorphic Arrays: A Novel VLSI Layout for Systolic Computers

Abstract This paper proposes a novel architecture for massively parallel systolic computers, which is based on results from lattice theory. In the proposed architecture, each processor is connected to four other processors via constant-length wires in a regular borderless pattern. The mapping of processes to processors is continuous, and the architecture guarantees exceptional load uniformity for rectangular process arrays of arbitrary sizes. In addition, no time-sharing is ever required when the ratio of processes to processors is smaller than 1 √5 .

Amos Fiat | Adi Shamir

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