A fast symbolic computation approach to statistical analysis of mesh networks with multiple sources

Mesh circuits typically consist of many resistive links and many sources. Accurate analysis of massive mesh networks is demanding in the current integrated circuit design practice, yet their computation confronts numerous challenges. When variation is considered, mesh analysis becomes a much harder task. This paper proposes a symbolic computation technique that can be applied to the moment-based analysis of mesh networks with multiple sources. The variation issues are easily taken care of by a structured computation mechanism, which can naturally facilitate sensitivity based analysis. Applications are addressed by applying the computation technique to a set of mesh circuits with varying sizes.

[1]  Rob A. Rutenbar,et al.  Fast interval-valued statistical modeling of interconnect and effective capacitance , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Bo Hu,et al.  On symbolic model order reduction , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  R. A. Rohrer Circuit partitioning simplified , 1988 .

[4]  David Blaauw,et al.  A simple metric for slew rate of RC circuits based on two circuit moments , 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  David Blaauw,et al.  Statistical interconnect metrics for physical-design optimization , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Rajendran Panda,et al.  Analysis of large clock meshes via Harmonic-weighted model order reduction and port sliding , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[8]  Wu-Shiung Feng,et al.  Applications of tree/link partitioning for moment computations of general lumped RLC networks with resistor loops , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[9]  Zhigang Hao,et al.  Symbolic techniques for statistical timing analysis of RCL mesh networks with resistor loops , 2009, Proceedings of the 2009 12th International Symposium on Integrated Circuits.

[10]  Chandramouli V. Kashyap,et al.  A two moment RC delay metric for performance optimization , 2000, ISPD '00.

[11]  Rajeev Murgai,et al.  A sliding window scheme for accurate clock mesh analysis , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[12]  Zhigang Hao,et al.  Sensitivity approach to statistical signal integrity analysis of coupled interconnect trees , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

[13]  K.A. Jenkins,et al.  A clock distribution network for microprocessors , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[14]  Zeng Jun-Kuei,et al.  Deep submicron interconnect timing model with quadratic random variable analysis , 2008 .

[15]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluation using AWE , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Ernest S. Kuh,et al.  Exact moment matching model of transmission lines and application to interconnect delay estimation , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[17]  Wu-Shiung Feng,et al.  Moment computations for R(L)C interconnects with multiple resistor loops using ROBDD techniques , 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

[18]  Chandramouli V. Kashyap,et al.  Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.