A new code generation algorithm for 2-offset producer order queue computation model

Queue computing is an attractive alternative for the compulsive demand of high-performance architectures. Code generation for queue machines has some problems but the solutions have not been studied thoroughly. A new parallel queue computation model, 2-offset P-Code queue computation model, is presented together with a new code generation algorithm. The code generation algorithm takes leveled DAGs as input and produces 2-offset P-Code assembly. We also developed a queue compiler to evaluate the new algorithm and compiled a set of C language benchmark programs for the 2-offset P-Code. The queue compiler generates between 8.55% less instructions and 10.55% more instructions than an actual MIPS32 compiler for the compiled programs.

[1]  Tsutomu Yoshinaga,et al.  Parallel Queue Processor Architecture Based on Produced Order Computation Model , 2005, The Journal of Supercomputing.

[2]  David W. Wall,et al.  Limits of instruction-level parallelism , 1991, ASPLOS IV.

[3]  Herman Schmit,et al.  Queue machines: hardware compilation in hardware , 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[4]  Masahiro Sowa,et al.  Design and architecture for an embedded 32-bit QueueCore , 2006, J. Embed. Comput..

[5]  Lenwood S. Heath,et al.  Stack and Queue Layouts of Directed Planar Graphs , 1993, Planar Graphs.

[6]  Diego Novillo Tree SSA A New Optimization Infrastructure for GCC , 2004 .

[7]  Tsutomu Yoshinaga,et al.  High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core , 2006, The Journal of Supercomputing.

[8]  Donald E. Knuth,et al.  The art of computer programming: V.1.: Fundamental algorithms , 1997 .

[9]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[10]  Masahiro Sowa,et al.  Design of a superscalar processor based on queue machine computation model , 1999, 1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368).

[11]  Arnold L. Rosenberg,et al.  Scheduling Tree-Dags Using FIFO Queues: A Control-Memory Trade-Off , 1996, J. Parallel Distributed Comput..

[12]  Donald Ervin Knuth,et al.  The Art of Computer Programming , 1968 .

[13]  Huibin Shi,et al.  Investigating available instruction level parallelism for stack based machine architectures , 2004 .

[14]  J. Bruno,et al.  The Generation of Optimal Code for Stack Machines , 1975, JACM.

[15]  Philip Koopman,et al.  A Preliminary Exploration of Optimized Stack Code Generation , 1995 .

[16]  Lenwood S. Heath,et al.  Stack and Queue Layouts of Directed Acyclic Graphs: Part I , 1999, SIAM J. Comput..

[17]  Jr. Philip J. Koopman,et al.  Stack computers: the new wave , 1989 .

[18]  Bruno R. Preiss,et al.  Data flow on a queue machine , 1985, ISCA 1985.