Analysis of a High-Speed Interconnection Network

A thorough routing analysis of a switching network called the spherical switching network for high-speed applications is presented in this paper. The spherical switching network has a cyclic, regular, and highly expandable structure with a simple self-routing scheme. The network is constructed with fixed-size switch elements regardless of the size of the network. Each switch element consists of a carefully-selected sized 9 input/output crossbar and a local controller. One of the nine pairs of links is external and carries the external traffic, and the other eight pairs are internal. The contention resolution in each switch element is based on deflection of losing packets and incremental priority of packets. The switch elements do not utilize any buffering within the network. The analysis shows that this network clearly outperforms typical interconnection networks currently being deployed in practical switches and routers such as Banyan network. In order to keep the number of deflections low, each incoming external link is connected to a buffer with flow control capabilities. Due to the special arrangement of interconnections in the network, a much larger number of shortest paths between each pair of source/destination exists. The related analysis for finding the number of hops and shortest paths appear in this paper.

[1]  Albert G. Greenberg,et al.  Sharp approximate models of deflection routing in mesh networks , 1993, IEEE Trans. Commun..

[2]  N. Mirfakhraei.  Performance analysis of a large-scale switching system for high-speed ATM networks , 1994, 1994 IEEE GLOBECOM. Communications: The Global Bridge.

[3]  W. David Sincoskie,et al.  Sunshine: A High-Performance Self-Routing Broadband Packet Switch Architecture , 1991, IEEE J. Sel. Areas Commun..

[4]  Nick McKeown,et al.  Matching output queueing with a combined input output queued switch , 1999, IEEE INFOCOM '99. Conference on Computer Communications. Proceedings. Eighteenth Annual Joint Conference of the IEEE Computer and Communications Societies. The Future is Now (Cat. No.99CH36320).

[5]  A. Botta,et al.  A High Speed CMOS Circuit for 1.244 Gb/s 16×16 ATM Switching , 1991, ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference.

[6]  Tony T. Lee.  A modular architecture for very large packet switches , 1990, IEEE Trans. Commun..

[7]  Alan Huang,et al.  Starlite: a wideband digital switch , 1991 .

[8]  Jonathan S. Turner.  An optimal nonblocking multicast virtual circuit switch , 1994, Proceedings of INFOCOM '94 Conference on Computer Communications.

[9]  Charles Clos,et al.  A study of non-blocking switching networks , 1953 .

[10]  Sibabrata Ray,et al.  MSXmin: a modular multicast ATM packet switch with low delay and hardware complexity , 2000, TNET.

[11]  T. Suzuki,et al.  Output‐buffer switch architecture for asynchronous transfer mode , 1989 .

[12]  V. Benes,et al.  Mathematical Theory of Connecting Networks and Telephone Traffic. , 1966 .

[13]  David G. Cantor,et al.  On non-blocking switching networks , 1971, Networks.

[14]  N. Mirfakhraei.  Design of a CMOS buffered switch for a Gigabit ATM switching network , 1995 .

[15]  Daniel M. Dias,et al.  Analysis and Simulation of Buffered Delta Networks , 1981, IEEE Transactions on Computers.

[16]  Reza Rooholamini,et al.  Finding the right ATM switch for the market , 1994, Computer.

[17]  Wu-Yuin Hwang,et al.  An efficient cell-scheduling algorithm for multicast ATM switching systems , 2000, TNET.

[18]  A. K. Choudhury,et al.  Performance analysis of deflection routing in the Manhattan Street network , 1991, ICC 91 International Conference on Communications Conference Record.

[19]  Jonathan S. Turner,et al.  Queueing analysis of buffered switching networks , 1993, IEEE Trans. Commun..

[20]  Keith W. Ross,et al.  On Nonblocking Multirate Interconnection Networks , 1991, SIAM J. Comput..

[21]  Jonathan S. Turner,et al.  Design of a gigabit ATM switch , 1997, Proceedings of INFOCOM '97.

[22]  R. Muller,et al.  A Multifunctional High Speed Switching Element for ATM Applications , 1991, ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference.

[23]  Nicholas F. Maxemchuk,et al.  Effect of a finite reassembly buffer on the performance of deflection routing , 1991, ICC 91 International Conference on Communications Conference Record.

[24]  Anthony S. Acampora,et al.  The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet Switching , 1987, IEEE J. Sel. Areas Commun..

[25]  Fouad A. Tobagi,et al.  Fast packet switch architectures for broadband integrated services digital networks , 1990, Proc. IEEE.

[26]  Riccardo Melen,et al.  Optimal cost/performance design of ATM switches , 1992, [Proceedings] IEEE INFOCOM '92: The Conference on Computer Communications.

[27]  Kenneth E. Batcher,et al.  Sorting networks and their applications , 1968, AFIPS Spring Joint Computing Conference.

[28]  Hamid Ahmadi,et al.  A survey of modern high-performance switching techniques , 1989, IEEE J. Sel. Areas Commun..

[29]  Maxemchuk.  The Manhattan street network , 1985 .

[30]  Gérard Hébuterne.  Traffic Flow in Switching Systems , 1987 .

[31]  Jonathan S. Turner,et al.  Design of a broadcast packet switching network , 1988, IEEE Trans. Commun..

[32]  Ted H. Szymanski,et al.  Markov chain analysis of packet-switched banyans with arbitrary switch sizes, queue sizes, link multiplicities and speedups , 1989, IEEE INFOCOM '89, Proceedings of the Eighth Annual Joint Conference of the IEEE Computer and Communications Societies.

[33]  Jonathan S. Turner,et al.  Improved queueing analysis of shared buffer switching networks , 1993, TNET.

[34]  Paolo Giacomazzi,et al.  Shuffle interconnection networks with deflection routing for ATM switching: The Closed-Loop Shuffleout , 1991, IEEE INFCOM '91. The conference on Computer Communications. Tenth Annual Joint Comference of the IEEE Computer and Communications Societies Proceedings.