The impact of technology scaling on ESD robustness and protection circuit design

The trends in ESD robustness as a function of technology scaling, for feature sizes down to 0.25 /spl mu/m, have been experimentally determined using single finger nMOS transistors and full ESD protection circuits. It is shown that as feature sizes are reduced, good ESD performance can be obtained provided the negative effects of the shallower junctions are offset by the positive effects of the reduction in the effective channel lengths. Hence, processes and protection circuits with feature sizes as small as 0.25 /spl mu/m can be developed without degrading ESD robustness. >

[1]  M. G. Armendariz,et al.  Surprising patterns of CMOS susceptibility to ESD and implications on long-term reliability , 1980 .

[2]  Chenming Hu,et al.  An analytical breakdown model for short-channel MOSFET's , 1982, IEEE Transactions on Electron Devices.

[3]  R. Muller,et al.  VIA-4 avalanche-induced breakdown mechanisms in short-channel MOSFETs , 1982, IEEE Transactions on Electron Devices.

[4]  G. Simmons,et al.  Snapback Induced Gate Dielectric Breakdown in Graded Junction MOS Structures , 1984, 22nd International Reliability Physics Symposium.

[5]  C. Hu,et al.  Dynamic stressing of thin oxides , 1986, 1986 International Electron Devices Meeting.

[6]  C. Duvvury,et al.  ESD Protection Reliability in 1μM CMOS Technologies , 1986, 24th International Reliability Physics Symposium.

[7]  T.C. Holloway,et al.  An 0.8µm CMOS technology for high performance logic applications , 1987, 1987 International Electron Devices Meeting.

[8]  D. A. Bell,et al.  0.5 micron CMOS for high performance at 3.3 V , 1988, Technical Digest., International Electron Devices Meeting.

[9]  E. A. Amerasekera,et al.  An investigation of the nature and mechanisms of ESD damage in NMOS transistors , 1989 .

[10]  C. Duvvury,et al.  ESD phenomena in graded junction devices , 1989 .

[11]  T. Polgreen,et al.  A low-voltage triggering SCR for on-chip ESD protection at output and input pads , 1990, IEEE Electron Device Letters.

[12]  C. Hu,et al.  High-current snapback characteristics of MOSFETs , 1990 .

[13]  A. Amerasekera,et al.  Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters , 1991 .

[14]  R. Chapman,et al.  High performance sub-half micron CMOS using rapid thermal processing , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[15]  C. Duvvury,et al.  Achieving uniform nMOS device power distribution for sub-micron ESD reliability , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[16]  Amitava Chatterjee,et al.  Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow , 1992 .

[17]  J. Bruines,et al.  Suppression of soft failures in a submicron CMOS process , 1993 .

[18]  R. Chapman,et al.  Oxide thickness dependence of inverter delay and device reliability for 0.25 /spl mu/m CMOS technology , 1993, Proceedings of IEEE International Electron Devices Meeting.

[19]  C. Duvvury,et al.  ESD: a pervasive reliability concern for IC technologies , 1993 .

[20]  A. Amerasekera,et al.  Prediction of ESD robustness in a process using 2D device simulations , 1993, 31st Annual Proceedings Reliability Physics 1993.

[21]  Amitava Chatterjee,et al.  An investigation of BiCMOS ESD protection circuit elements and applications in submicron technologies , 1993 .

[22]  D. B. Krakauer.  ESD protection in a 3.3 V sub-micron silicided CMOS technology , 1993 .

[23]  Bernard G. Carbajal,et al.  A successful HBM ESD protection circuit for micron and sub-micron level CMOS , 1993 .

[24]  D. Lin.  ESD sensitivity and VLSI technology trends: thermal breakdown and dielectric breakdown , 1994 .

[25]  J. Bruines,et al.  Suppression and origin of soft ESD failures in a submicron CMOS process , 1994 .

[26]  R. Chapman,et al.  Technology design for high current and ESD robustness in a deep submicron CMOS process , 1994, IEEE Electron Device Letters.

[27]  Steven H. Voldman,et al.  Scaling, optimization and design considerations of electrostatic discharge protection circuits in CMOS technology , 1994 .