A simple EEPROM cell using twin polysilicon thin film transistors

A planar twin polysilicon thin film transistor (TFT) EEPROM cell fabricated with a simple low temperature (/spl les/600/spl deg/C) process is demonstrated in this work. The gate electrodes of the two TFT's are connected to form the floating gate of the cell, while the source and drain of the larger TFT are connected to form the control gate. The cell is programmed and erased by Fowler-Nordheim tunneling. The threshold voltage of the cell can be shifted by as much as 8 V after programming. This new EEPROM cell can dramatically reduce the cost of production by reducing manufacturing complexity.<<ETX>>

[1]  S. Koyama.  A novel cell structure for giga-bit EPROMs and flash memories using polysilicon thin film transistors , 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.

[2]  N. Asamoto,et al.  A Planar Type Eeprom Cell Structure By Standard CMOS Process And Applications , 1993, Symposium 1993 on VLSI Technology.