A 610-MHz FIR Filter Using Rotary Clock Technique

This paper presents a low-power and high-speed finite impulse response (FIR) filter design. The uniqueness of our design is that it utilizes a resonant clocking technique, called rotary clock. Through custom design steps such as clock skew assignments, register placement, multi-phase clock routing, the proposed FIR filter is seamlessly integrated with rotary clock technique. It uses the spatially distributed multiple clock phases of rotary clock and achieves the full rotary clock power saving potential. Our design is fully digital and generated using CMOS standard cells in 0.18 mum technology. We show that our rotary clock based FIR filter can operate successfully at 610 MHz, providing a throughput of 39 Gbps. In comparison with the conventional clock tree based design, our design achieves a 34.6% clocking power saving and a 12.8% overall circuit power saving. To our knowledge, our design is the first rotary clock based non-trivial digital circuit ever reported.