Testing VLSI circuits from VHDL descriptions

The authors describe a new testing strategy for VLSI digital circuits, based on the use of a hardware description language as an input file. The advantages of this method are pointed out. Circuits are described using the standard hardware description language VHDL. A behavioral fault model is proposed, defined as a perturbation of the VHDL code, and evaluated using a classical fault model as a reference. A description of all the tools required to achieve a complete testing system for high complexity circuits is provided. The approaches that have appeared in previous references are discussed.<<ETX>>