The engineering of BSIM for the nano-technology era and beyond

This paper presents the current status of the forth generation BSIM model and issues of modeling CMOS based devices with nanometer dimensions. Due to the divergence of device structures in sub-0.1 m gate length, it is more and more difficult to describe the device physics accurately and efficiently. In order to have a practical model with enough flexibility to accommodate a wide variety of technologies, vigorous engineering techniques have to be incorporated. At the same time, modern computer program techniques including numerical differentiation and parallel model evaluation are considered to shorten model development time. The tradeoffs between computation efficiency and development time will be discussed. Methodologies to design next generation extendible device models with advanced computer programming techniques are proposed.