Hypergraph Partitioning and Clustering
暂无分享,去创建一个
[1] Katherine A. Yelick,et al. Optimizing Sparse Matrix Vector Multiplication on SMP , 1999, SIAM Conference on Parallel Processing for Scientific Computing.
[2] Charles J. Alpert,et al. The ISPD98 circuit benchmark suite , 1998, ISPD '98.
[3] Sheila A. McIlraith,et al. Partition-based logical reasoning for first-order and propositional theories , 2005, Artif. Intell..
[4] C. Alpert,et al. Multi-Way Partitioning Via Spacefilling Curves and Dynamic Programming , 1994, 31st Design Automation Conference.
[5] Andrew B. Kahng,et al. Optimal partitioners and end-case placers for standard-cell layout , 1999, ISPD '99.
[6] Sung-Woo Hur,et al. Relaxation and clustering in a local search framework: application to linear placement , 1999, DAC '99.
[7] Balakrishnan Krishnamurthy,et al. An Improved Min-Cut Algonthm for Partitioning VLSI Networks , 1984, IEEE Transactions on Computers.
[8] Vipin Kumar,et al. Hypergraph Based Clustering in High-Dimensional Data Sets: A Summary of Results , 1998, IEEE Data Eng. Bull..
[9] Igor L. Markov,et al. MINCE : A Static Global Variable-Ordering for SAT Search and BDD Manipulation , 2000 .
[10] Andrew B. Kahng,et al. A new approach to effective circuit clustering , 1992, ICCAD.
[11] Randal E. Bryant,et al. Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic , 1999, CHARME.
[12] Shantanu Dutt,et al. VLSI circuit partitioning by cluster-removal using iterative improvement techniques , 1996, Proceedings of International Conference on Computer Aided Design.
[13] Kurt Keutzer,et al. Why is ATPG easy? , 1999, DAC '99.
[14] David S. Johnson,et al. Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .
[15] Andrew B. Kahng,et al. A hybrid multilevel/genetic approach for circuit partitioning , 1996, Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems.
[16] Dennis J.-H. Huang,et al. On implementation choices for iterative improvement partitioning algorithms , 1995, Proceedings of EURO-DAC. European Design Automation Conference.
[17] Andrew B. Kahng,et al. Hypergraph partitioning with fixed vertices , 1999, DAC '99.
[18] Sheila A. McIlraith,et al. Practical Partition-Based Theorem Proving for Large Knowledge Bases , 2003, IJCAI.
[19] Andrew B. Kahng,et al. Improved algorithms for hypergraph bipartitioning , 2000, ASP-DAC '00.
[20] Andrew B. Kahng,et al. Recent directions in netlist partitioning: a survey , 1995, Integr..
[21] R. M. Mattheyses,et al. A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.
[22] Franc BrglezApril. Design of Experiments to Evaluate CAD Algorithms: Which Improvements Are Due to Improved Heuristic and Which Are Merely Due to Chance? , 1998 .
[23] Andrew B. Kahng,et al. Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning , 1999, ALENEX.
[24] Brian W. Kernighan,et al. An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..
[25] George Karypis,et al. C HAMELEON : A Hierarchical Clustering Algorithm Using Dynamic Modeling , 1999 .
[26] Vipin Kumar,et al. Multilevel k-way hypergraph partitioning , 1999, DAC '99.
[27] Joao Marques-Silva,et al. GRASP: A Search Algorithm for Propositional Satisfiability , 1999, IEEE Trans. Computers.
[28] Martin D. F. Wong,et al. Efficient network flow based min-cut balanced partitioning , 1994, ICCAD.
[29] Gaetano Borriello,et al. An evaluation of bipartitioning techniques , 1995, Proceedings Sixteenth Conference on Advanced Research in VLSI.
[30] Sharad Malik,et al. Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[31] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[32] William Aiello,et al. Sparse Matrix Computations on Parallel Processor Arrays , 1993, SIAM J. Sci. Comput..
[33] Sung-Woo Hur,et al. Mongrel: hybrid techniques for standard cell placement , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[34] J. P. Grossman,et al. Characterization and parameterized random generation of digital circuits , 1996, 33rd Design Automation Conference Proceedings, 1996.
[35] Rob A. Rutenbar,et al. A comparative study of two Boolean formulations of FPGA detailed routing constraints , 2001, IEEE Transactions on Computers.
[36] Andrew B. Kahng,et al. Multilevel circuit partitioning , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[37] Vipin Kumar,et al. Analysis of Multilevel Graph Partitioning , 1995, Proceedings of the IEEE/ACM SC95 Conference.
[38] Chung-Kuan Cheng,et al. A gradient method on the initial partition of Fiduccia-Mattheyses algorithm , 1995, ICCAD.
[39] Roy L. Russo,et al. On a Pin Versus Block Relationship For Partitions of Logic Graphs , 1971, IEEE Transactions on Computers.
[40] Petru Eles,et al. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search , 1997, Des. Autom. Embed. Syst..
[41] Bruce Hendrickson,et al. A Multi-Level Algorithm For Partitioning Graphs , 1995, Proceedings of the IEEE/ACM SC95 Conference.
[42] Igor L. Markov,et al. Faster SAT and smaller BDDs via common function structure , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).
[43] Shashi Shekhar,et al. Multilevel hypergraph partitioning: application in VLSI domain , 1997, DAC.
[44] Andrew B. Kahng,et al. Hypergraph partitioning for VLSI CAD: methodology for heuristic development, experimentation and reporting , 1999, DAC '99.
[45] Shantanu Dutt,et al. Partitioning using second-order information and stochastic-gainfunctions , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[46] Jonathan Rose,et al. Characterization and parameterized random generation of digital circuits , 1996, DAC '96.
[47] Laura A. Sanchis,et al. Multiple-Way Network Partitioning with Different Cost Functions , 1993, IEEE Trans. Computers.
[48] Sung Kyu Lim,et al. Edge separability based circuit clustering with application to circuit partitioning , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).
[49] Shashi Shekhar,et al. Multilevel hypergraph partitioning: applications in VLSI domain , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[50] Yinyu Ye,et al. Application of Semidefinite Programming to Circuit Partitioning , 2000 .
[51] Jason Cong,et al. Large scale circuit partitioning with loose/stable net removal and signal flow based clustering , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[52] C. Leonard Berman,et al. Circuit width, register allocation, and ordered binary decision diagrams , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[53] Shantanu Dutt,et al. Partitioning using second-order information and stochastic-gain functions , 1998, ISPD '98.