论文信息 - A cost-effective digital front-end realization for 20-bit ΣΔ DAC in 0.13 μm CMOS

A cost-effective digital front-end realization for 20-bit ΣΔ DAC in 0.13 μm CMOS

A cost-effective digital front-end used in 20-bit ΣΔ DAC for audio applications is described in this paper. The digital front-end is composed of an interpolator and a ΣΔ modulator (DSM). Mixed-radix number representation (MRNR) algorithm combined with poly-phase filtering technique and high efficiency hardware realization method are used to achieve high data conversion precision and reduce the area of the interpolator. A single bit distributed feedback structure is adopted for DSM to shape quantization noise. The digital front-end works at a 1.2-V power supply and is implemented in 0.13 μm CMOS process, which occupies a die area of 0.63 mm2 and achieves more than 130 dB dynamic range.

Liyuan Liu | Dongmei Li | Run Chen

[1] Alan V. Oppenheim,et al. Discrete-time signal processing (2nd ed.) , 1999 .

[2] Truong Q. Nguyen,et al. A 'trick' for the design of FIR half-band filters , 1987 .

[3] L. Rabiner,et al. An approach to the approximation problem for nonrecursive digital filters , 1970 .

[4] G. Temes. Delta-sigma data converters , 1994 .

[5] Yoshiaki Tadokoro,et al. A simple design of FIR filters with powers-of-two coefficients , 1988 .

[6] Jianlin Li,et al. Multiplier-free realizations for FIR multirate converters based on mixed-radix number representation , 1997, IEEE Trans. Signal Process..

[7] Sawasd Tantaratana,et al. Signed-digit-based multiplier-free realizations for multirate converters , 1995, IEEE Trans. Signal Process..

[8] R. Schreier,et al. Delta-sigma data converters : theory, design, and simulation , 1997 .