Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits

A method of test pattern generation for multiple stuck-at faults in VLSI circuits, using genetic algorithm is proposed. The test patterns were earlier generated for single stuck at faults only but in the proposed work, multiple faults are considered and fault masking is also taken into account when faults are injected. The test patterns to detect the faults are the binary values given as inputs to the circuit under test. These patterns should be compact and also should have minimum switching among them to reduce the test power. Genetic Algorithms (GA) is a search technique to find solutions to optimization and search problems. Hence the proposed work uses GA to generate test patterns. Here the chromosomes in GA are substituted for the test patterns. The test patterns are initialized randomly and their fitness value is evaluated. Now GA operators like selection, crossover and mutation are applied on this initial set to reproduce better test patterns. These generated test patterns are reordered using reordering techniques, don't cares filled by filling techniques to reduce the switching activity among them thus reducing the test power.

[1]  Hiroshi Takahashi,et al.  On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[3]  Guangzhao Zhang,et al.  Neural Network Approach for Multiple Fault Test of Digital Circuit , 2006, Sixth International Conference on Intelligent Systems Design and Applications.

[4]  Malgorzata Marek-Sadowska,et al.  Analysis and methodology for multiple-fault diagnosis , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[6]  Kwang-Ting Cheng,et al.  Multiple-Fault Diagnosis Based on Single-Fault Activation and Single-Output Observation , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[7]  Irith Pomeranz,et al.  On improving genetic optimization based test generation , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[8]  Malgorzata Marek-Sadowska,et al.  An efficient and effective methodology on the multiple fault diagnosis , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[9]  Malgorzata Marek-Sadowska,et al.  Multiple fault diagnosis using n-detection tests , 2003, Proceedings 21st International Conference on Computer Design.

[10]  M. Ray Mercer,et al.  Using logic models to predict the detection behavior of statistical timing defects , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[11]  Serge Pravossoudovitch,et al.  Reducing power consumption during test application by test vector ordering , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[12]  Leendert M. Huisman.  Diagnosing arbitrary defects in logic designs using single location at a time (SLAT) , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.