12-Gb/s low-power voltage-mode driver for multi-standard serial-link applications

This paper presents a 12-Gb/s power-efficient voltage-mode driver for multi-standard serial-link applications. The proposed driver combines the advantages of voltage-mode drivers and those of variable-output-swing ones into a single architecture for multi-standard operation. This is achieved by having a reconfigurable pull-up network and a fixed shared pull-down network. In addition, this technique is combined with a modified 3-tap feed-forward equalizer (FFE) to support the de-emphasis required by several standards. The proposed driver is implemented using 65-nm CMOS technology and supports a variable output voltage swing of 0.3 Vpp to 1 Vpp, while achieving data rates ranging from 1.5 Gb/s to 12 Gb/s. The driver consumes 1.25 mW for an output swing of 0.5 Vpp, which is the minimum achievable power consumption for voltage-mode drivers.

[1]  John T. Stonick,et al.  A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS , 2006, IEEE Custom Integrated Circuits Conference 2006.

[2]  K. Abe,et al.  An ASIC-Ready 1.25–6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[3]  Yue Lu,et al.  Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters , 2013, IEEE Journal of Solid-State Circuits.

[4]  Kee-Won Kwon,et al.  A low-swing AC- and DC- coupled voltage-mode driver with pre-emphasis , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

[5]  Thomas Toifl,et al.  A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With $≪ -$16 dB Return Loss Over 10 GHz Bandwidth , 2008, IEEE Journal of Solid-State Circuits.

[6]  Ayal Shoval,et al.  An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology , 2011, 2011 IEEE International Solid-State Circuits Conference.

[7]  A. Wang,et al.  A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications , 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).