Yield Evaluation of 10-kA/cm $^{2}$ Nb Multi-Layer Fabrication Process Using Conventional Superconducting RAMs

To achieve larger scale and higher speed single flux quantum (SFQ) circuits, we have been developing a 10-kA/cm2 Nb multi-layer fabrication process composed of more than six pla- narized Nb layers, an Nb/AlOx /Nb junction layer, a Mo resistor layer, and SiO2 insulator layers. To evaluate reliability of the fabrication process, we have designed superconducting random access memories (RAMs) with four different memory capacities: 256, IK, 4 K, and 16 K bits. Although the circuit configuration of these RAMs is almost the same as that of previously developed ones that have conventional latching devices, we modified the circuit parameters and layout design based on specifications of the new fabrication process. We have obtained operations for the 256-bit RAM with a bit yield of 100%, the lK-bit RAM with a bit yield of 99.8%, and the 4K-bit RAM with a bit yield of 96.7%. The number of defects in the 4K-bit RAM was estimated to be approximately 10. We confirmed that evaluations using the RAMs were effective at detecting defects due to the fabrication process.

[1]  Shuichi Nagasawa,et al.  Reliability evaluation of Nb 10 kA/cm2 fabrication process for large-scale SFQ circuits , 2005 .

[2]  Shuichi Nagasawa,et al.  Design of all-dc-powered high-speed single flux quantum random access memory based on a pipeline structure for memory cell arrays , 2006 .

[3]  Shuichi Nagasawa,et al.  Fabrication technology for a high-density Josephson LSI using an electron cyclotron resonance etching technique and a bias-sputtering planarization , 1996 .

[4]  S.. Nagasawa,et al.  Improvement of Fabrication Process for 10-${\rm kA/cm}^{2}$ Multi-Layer Nb Integrated Circuits , 2007, IEEE Transactions on Applied Superconductivity.

[5]  Shuichi Nagasawa,et al.  Pattern-Size-Free Planarization for Multilayered Large-Scale SFQ Circuits , 2003 .

[6]  Shuichi Nagasawa,et al.  Planarized multi-layer fabrication technology for LTS large-scale SFQ circuits , 2003 .

[7]  M. Hidaka,et al.  Fabrication process of planarized multi-layer Nb integrated circuits , 2005, IEEE Transactions on Applied Superconductivity.

[8]  S. Tahara,et al.  Fabrication technology for high-density Josephson integrated circuits using mechanical polishing planarization , 1999, IEEE Transactions on Applied Superconductivity.

[9]  Shuichi Tahara,et al.  Investigation of SFQ integrated circuits using Nb fabrication technology , 1999 .

[10]  S. Tahara,et al.  A 380 ps, 9.5 mW Josephson 4-Kbit RAM operated at a high bit yield , 1995, IEEE Transactions on Applied Superconductivity.

[11]  Shuichi Nagasawa,et al.  Development of advanced Nb process for SFQ circuits , 2004 .

[12]  Shuichi Tahara,et al.  Fabrication Technology for Nb Integrated Circuits , 2001 .