Issues, achievements and challenges towards integration of high-k dielectrics

Once the thickness of the gate dielectric layer in CMOS devices gets thinner than 1.2 nm, excessive gate leakage due to direct tunneling makes the use of alternative materials obligatory. Candidate high-k materials are metal oxides such as Al2O3, ZrO2 and HfO2 as well as their mixtures. Very promising results have been reported world-wide. Here, however, we show that there are a number of issues related to materials and electrical characteristics as well as to processing which are not always recognized and that necessitate more work to find solutions. Among these are problems with density, interface layer growth and island formation which are clearly related to the deposition process. Also thermal instabilities as well as interactions between the high-k material and poly-Si need attention. Further possible show-stoppers are electrical reliability issues and strongly reduced carrier mobility.