Ten Years of Building Broken Chips: The Physics and Engineering of Inexact Computing

Well over a decade ago, many believed that an engine of growth driving the semiconductor and computing industries---captured nicely by Gordon Moore’s remarkable prophecy (Moore’s law)---was speeding towards a dangerous cliff-edge. Ranging from expressions of concern to doomsday scenarios, the exact time when serious hurdles would beset us varied quite a bit---some of the more optimistic warnings giving Moore’s law until. Needless to say, a lot of people have spent time and effort with great success to find ways for substantially extending the time when we would encounter the dreaded cliff-edge, if not avoiding it altogether. Faced with this issue, we started approaching this in a decidedly different manner---one which suggested falling off the metaphorical cliff as a design choice, but in a controlled way. This resulted in devices that could switch and produce bits that are correct, namely of having the intended value, only with a probabilistic guarantee. As a result, the results could in fact be incorrect. Such devices and associated circuits and computing structures are now broadly referred to as inexact designs, circuits, and architectures. In this article, we will crystallize the essence of inexactness dating back to 2002 through two key principles that we developed: (i) that of admitting error in a design in return for resource savings, and subsequently (ii) making resource investments in the elements of a hardware platform proportional to the value of information they compute. We will also give a broad overview of a range of inexact designs and hardware concepts that our group and other groups around the world have been developing since, based on these two principles. Despite not being deterministically precise, inexact designs can be significantly more efficient in the energy they consume, their speed of execution, and their area needs, which makes them attractive in application contexts that are resilient to error. Significantly, our development of inexactness will be contrasted against the rich backdrop of traditional approaches aimed at realizing reliable computing from unreliable elements, starting with von Neumann’s influential lectures and further developed by Shannon-Weaver and others.

[1]  Lingamneni Avinash,et al.  Highly energy and performance efficient embedded computing through approximately correct arithmetic: a mathematical foundation and preliminary experimental validation , 2008, CASES '08.

[2]  Anantha P. Chandrakasan,et al.  Low power filtering using approximate processing for DSP applications , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[3]  Kaushik Roy,et al.  HERQULES: System level cross-layer design exploration for efficient energy-quality trade-offs , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[4]  Zhi-Hui Kong,et al.  Probabilistic CMOS ( PCMOS ) Logic for Nanoscale Circuit Design , 2009 .

[5]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[6]  Kaushik Roy,et al.  A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[7]  M. Forshaw,et al.  Architectures for reliable computing with unreliable nanodevices , 2001, Proceedings of the 2001 1st IEEE Conference on Nanotechnology. IEEE-NANO 2001 (Cat. No.01EX516).

[8]  Richard M. Karp,et al.  Probabilistic Analysis of Partitioning Algorithms for the Traveling-Salesman Problem in the Plane , 1977, Math. Oper. Res..

[9]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[10]  PalemKrishna,et al.  Ten Years of Building Broken Chips , 2013 .

[11]  Kaushik Roy,et al.  Process Variation Tolerant Low Power DCT Architecture , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[12]  Claude E. Shannon,et al.  A symbolic analysis of relay and switching circuits , 1938, Transactions of the American Institute of Electrical Engineers.

[13]  Wayne H. Wolf,et al.  Experimental analysis of sequence dependence on energy saving for error tolerant image processing , 2009, ISLPED.

[14]  Krishna V. Palem,et al.  Energy aware computing through probabilistic switching: a study of limits , 2005, IEEE Transactions on Computers.

[15]  Kaushik Roy,et al.  Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency , 2010, Design Automation Conference.

[16]  Douglas L. Jones,et al.  Scalable stochastic processors , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[17]  Ahmed M. Eltawil,et al.  Low-Power Multimedia System Design by Aggressive Voltage Scaling , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Lingamneni Avinash,et al.  Sustaining moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects , 2009, CASES '09.

[19]  David Blaauw,et al.  Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.

[20]  Krishna V. Palem,et al.  Energy aware algorithm design via probabilistic computing: from algorithms and models to Moore's law and novel (semiconductor) devices , 2003, CASES '03.

[21]  John Sartori,et al.  Stochastic computing: Embracing errors in architecture and design of processors and applications , 2011, 2011 Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES).

[22]  S. Borkar,et al.  A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[23]  K. E.,et al.  The Theory of Heat , 1929, Nature.

[24]  Krishna V. Palem,et al.  Probabilistic CMOS Technology: A Survey and Future Directions , 2006, 2006 IFIP International Conference on Very Large Scale Integration.

[25]  Bilge E. S. Akgul,et al.  A Probabilistic CMOS Switch and its Realization by Exploiting Noise , 2005 .

[26]  J. von Neumann,et al.  Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[27]  Lingamneni Avinash,et al.  What to do about the end of Moore's law, probably! , 2012, DAC Design Automation Conference 2012.

[28]  Christel Baier,et al.  Probabilistic ω-automata , 2012, JACM.

[29]  A. Turing.  On Computable Numbers, with an Application to the Entscheidungsproblem. , 1937 .

[30]  L. Kish.  End of Moore's law: thermal (noise) death of integration in micro and nano electronics , 2002 .

[31]  Muhannad S. Bakir,et al.  Nanoelectronics in retrospect, prospect and principle , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[32]  Sanu Mathew,et al.  A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[33]  Michael Engel,et al.  Classification-Based Improvement of Application Robustness and Quality of Service in Probabilistic Computer Systems , 2012, ARCS.

[34]  Naresh R. Shanbhag,et al.  Energy-efficient signal processing via algorithmic noise-tolerance , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[35]  Lingamneni Avinash,et al.  Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization , 2011, PATMOS.

[36]  Krishna V. Palem,et al.  Computational Proof as Experiment: Probabilistic Algorithms from a Thermodynamic Perspective , 2003, Verification: Theory and Practice.

[37]  Lingamneni Avinash,et al.  Energy parsimonious circuit design through probabilistic pruning , 2011, 2011 Design, Automation & Test in Europe.

[38]  Krishna V. Palem,et al.  Energy Aware Algorithm Design via Probabilistic Computing: From Algorithms and Models to Moore?s Law and Novel (Semiconductor) Devices , 2003, HiPC.

[39]  Pinar Ayhan,et al.  Probabilistic CMOS (PCMOS) in the Nanoelectronics Regime , 2007 .

[40]  Kaushik Roy,et al.  Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator , 2009, ISLPED.

[41]  Volker Strassen,et al.  A Fast Monte-Carlo Test for Primality , 1977, SIAM J. Comput..

[42]  Krishna V. Palem,et al.  An approach to energy-error tradeoffs in approximate ripple carry adders , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[43]  R. Landauer,et al.  Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..

[44]  Subhasish Mitra,et al.  ERSA: Error Resilient System Architecture for probabilistic applications , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[45]  Jason Schlessman,et al.  Accuracy-aware SRAM: A reconfigurable low power SRAM architecture for mobile multimedia applications , 2009, 2009 Asia and South Pacific Design Automation Conference.

[46]  W S McCulloch,et al.  A logical calculus of the ideas immanent in nervous activity , 1990, The Philosophy of Artificial Intelligence.

[47]  Lingamneni Avinash,et al.  Synthesizing Parsimonious Inexact Circuits through Probabilistic Design Techniques , 2013, TECS.

[48]  Richard M. Karp,et al.  Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling , 2012, CF '12.

[49]  Claude E. Shannon,et al.  Reliable Circuits Using Less Reliable Relays , 1956 .

[50]  Krishna V. Palem,et al.  Probabilistic system-on-a-chip architectures , 2007, TODE.

[51]  Pinar Korkmaz,et al.  Advocating Noise as an Agent for Ultra-Low Energy Computing: Probabilistic Complementary Metal-Oxide-Semiconductor Devices and Their Characteristics , 2006 .

[52]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[53]  Trevor N. Mudge,et al.  Power: A First-Class Architectural Design Constraint , 2001, Computer.

[54]  Aaron D. Wyner,et al.  Reliable Circuits Using Less Reliable Relays , 1993 .

[55]  Krishna V. Palem,et al.  Probabilistic arithmetic and energy efficient embedded signal processing , 2006, CASES '06.

[56]  George Boole,et al.  The Mathematical Analysis of Logic: Being an Essay Towards a Calculus of Deductive Reasoning , 2007 .

[57]  Lakshmi N. Chakrapani,et al.  A Probabilistic Boolean Logic and its Meaning , 2008 .

[58]  Azaria Paz,et al.  Probabilistic automata , 2003 .

[59]  Krishna V. Palem,et al.  Optimizing energy to minimize errors in dataflow graphs using approximate adders , 2010, CASES '10.

[60]  L. Szilard.  über die Entropieverminderung in einem thermodynamischen System bei Eingriffen intelligenter Wesen , 1929 .