Fast buffering for optimizing worst slack and resource consumption in repeater trees

We present a very fast algorithm for buffering repeater trees. We scan a given preliminary topology in a bottom-up fashion and insert buffers and inverters, respecting the parities of the sinks. Information obtained by preprocessing allows for very fast decisions. To bound the number of shielding repeaters, they are only used where necessary to maximize the worst slack. Furthermore, instead of using a fixed set of repeater positions, they are computed on the fly based on the already buffered subtrees. Another key feature of our algorithm is that we modify the preliminary topology while buffering in order to avoid parallel wires or too many inverters. Experimental results on industrial designs illustrate the speed, quality, practicality, and flexibility of our procedure. In particular, we buffer about 100,000 repeater trees per minute and obtain results that are close to the theoretical optimum in several respects.

[1]  Mark A. Franklin,et al.  Optimum buffer circuits for driving long uniform lines , 1991 .

[2]  Sachin S. Sapatnekar,et al.  Accurate estimation of global buffer delay within a floorplan , 2004, ICCAD 2004.

[3]  Weiping Shi,et al.  A fast algorithm for optimal buffer insertion , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Sachin S. Sapatnekar,et al.  Buffered Steiner trees for difficult instances , 2002 .

[5]  Jens Vygen,et al.  Slack in static timing analysis , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Chris C. N. Chu,et al.  A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization , 2000, ISPD '00.

[7]  Weiping Shi,et al.  An O(bn2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types , 2005, DATE.

[8]  Martin D. F. Wong,et al.  Closed form solution to simultaneous buffer insertion/sizing and wire sizing , 1997, ISPD '97.

[9]  Sachin S. Sapatnekar,et al.  Handbook of Algorithms for Physical Design Automation , 2008 .

[10]  Jens Vygen,et al.  Efficient generation of short and fast repeater tree topologies , 2006, ISPD '06.

[11]  Charles J. Alpert,et al.  A fast algorithm for identifying good buffer insertion candidate locations , 2004, ISPD '04.

[12]  Shiyan Hu,et al.  Fast Algorithms for Slew-Constrained Minimum Cost Buffering , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  L.P.P.P. van Ginneken,et al.  Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .

[14]  Chris C. N. Chu,et al.  FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Weiping Shi,et al.  An O(mn) time algorithm for optimal buffer insertion of nets with m sinks , 2006, ASP-DAC.

[16]  Josef Stoer,et al.  Numerische Mathematik 1 , 1989 .

[17]  Chung-Kuan Cheng,et al.  Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1996 .

[18]  Charles J. Alpert,et al.  Wire segmenting for improved buffer insertion , 1997, DAC.

[19]  Weiping Shi,et al.  An O(bn/sup 2/) time algorithm for optimal buffer insertion with b buffer types , 2005, Design, Automation and Test in Europe.

[20]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[21]  Edsger W. Dijkstra,et al.  A note on two problems in connexion with graphs , 1959, Numerische Mathematik.