Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set

units in unit-gate model. Besides the scaled residue numbers, the scaled integer in normal binary representation is also produced as a byproduct of this process, which saves the residue-to-binary converter when the binary representation of scaled integer is also required. Our experimental results show that the proposed RNS scaler is smaller and faster than the most area-efficient adder-based design and the fastest ROM-based design besides being the most power efficient among all scalers evaluated for the same three-moduli set.

[1]  Chip-Hong Chang,et al.  An efficient reverse converter for the 4-moduli set {2/sup n/ - 1, 2/sup n/, 2/sup n/ + 1, 2/sup 2n/ + 1} based on the new Chinese remainder theorem , 2003 .

[2]  Tarek Darwish,et al.  Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Stanislaw J. Piestrak.  Design of squarers modulo A with low-level pipelining , 2002 .

[4]  Thanos Stouraitis,et al.  New power-of-2 RNS scaling scheme for cell-based IC design , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Chip-Hong Chang,et al.  Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[6]  Costas Efstathiou,et al.  Area-time efficient modulo 2/sup n/-1 adder design , 1994 .

[7]  Chip-Hong Chang,et al.  A Reconfigurable Multi-Modulus Modulo Multiplier , 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

[8]  Chip-Hong Chang,et al.  A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits , 2005 .

[9]  Jianhao Hu,et al.  A 2n scaling scheme for signed RNS integers and its VLSI implementation , 2010, Science in China Series F: Information Sciences.

[10]  Mahesh Mehendale,et al.  Low power realization of residue number system based FIR filters , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[11]  Haridimos T. Vergos,et al.  Efficient modulo 2n+1 adder architectures , 2009, Integr..

[12]  Gian Carlo Cardarilli,et al.  Reducing power dissipation in FIR filters using the residue number system , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[13]  D. Bakalis,et al.  Shifter circuits for {2n+1, 2n, 2n−1} RNS , 2009 .

[14]  Yuke Wang,et al.  A study of the residue-to-binary converters for the three-moduli sets , 2003 .

[15]  Jianhao Hu,et al.  An Efficient RNS Scaler for Moduli Set , 2008, 2008 International Symposium on Information Science and Engineering.

[16]  B. Vinnakota,et al.  Fast conversion techniques for binary-residue number systems , 1994 .

[17]  Fred J. Taylor,et al.  Efficient scaling in the residue number system , 1989, International Conference on Acoustics, Speech, and Signal Processing,.

[18]  Chip-Hong Chang,et al.  A low complexity modulo 2n+1 squarer design , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

[19]  Chip-Hong Chang,et al.  A Residue-to-Binary Converter for a New Five-Moduli Set , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[20]  Haridimos T. Vergos,et al.  Modulo 2n±1 Adder Design Using Select-Prefix Blocks , 2003, IEEE Trans. Computers.

[21]  Stanislaw J. Piestrak.  Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders , 1994, IEEE Trans. Computers.

[22]  Dimitrios Soudris,et al.  A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[23]  Haridimos T. Vergos,et al.  Diminished-One Modulo 2n+1 Adder Design , 2002, IEEE Trans. Computers.

[24]  Antonio García,et al.  A Look-Up Scheme for Scaling in the RNS , 1999, IEEE Trans. Computers.

[25]  Gian Carlo Cardarilli,et al.  Low-power adaptive filter based on RNS components , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[26]  G.C. Cardarilli,et al.  Low Power and Low Leakage Implementation of RNS FIR Filters , 2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..

[27]  Chip-Hong Chang,et al.  Efficient reverse converters for four-moduli sets { 2n−1, 2n, 2n+1, 2n+1−1} and {2n−1, 2n, 2n+1, 2n−1−1} , 2005 .

[28]  Richard Conway,et al.  Fast Converter for 3 Moduli RNS Using New Property of CRT , 1999, IEEE Trans. Computers.

[29]  Jozef Zurada,et al.  Effective RNS scaling algorithm with the Chinese remainder theorem decomposition , 1993, Proceedings of IEEE Pacific Rim Conference on Communications Computers and Signal Processing.

[30]  Maria Cristina Pinotti,et al.  Fast base extension and precise scaling in RNS for look-up table implementations , 1995, IEEE Trans. Signal Process..

[31]  Richard Conway,et al.  Improved RNS FIR filter architectures , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[32]  Ramdas Kumaresan,et al.  A fast and accurate RNS scaling technique for high speed signal processing , 1989, IEEE Trans. Acoust. Speech Signal Process..

[33]  Zenon D. Ulman,et al.  Highly parallel, fast scaling of numbers in nonredundant residue arithmetic , 1998, IEEE Trans. Signal Process..

[34]  Ahmad A. Hiasat,et al.  High-Speed and Reduced-Area Modular Adder Structures for RNS , 2002, IEEE Trans. Computers.

[35]  Haridimos T. Vergos,et al.  Fast modulo 2n+1 multi-operand adders and residue generators , 2010, Integr..

[36]  Braden Phillips,et al.  Fast Scaling in the Residue Number System , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[37]  Hong Shen,et al.  Adder based residue to binary number converters for (2n-1, 2n, 2n+1) , 2002, IEEE Trans. Signal Process..

[38]  Gian Carlo Cardarilli,et al.  Tradeoffs between residue number system and traditional FIR filters , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[39]  A. Nannarelli,et al.  Implementation of digital filters in carry-save residue number system , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).