Estimating and Mitigating Aging Effects in Routing Network of FPGAs

In this paper, we present a comprehensive analysis of the impact of aging on the interconnection network of field-programmable gate arrays (FPGAs) and propose novel approaches to mitigate the aging effects on the routing network. We first show the insignificant impact of aging on data integrity of FPGAs, i.e., static noise margin and soft error rate of the configuration cells, as well as we show the negligible impact of the mentioned degradations on the FPGA performance. As such, we focus on the performance degradation of datapath transistors. In this regard, we propose a routing accompanied by a placement algorithm that prevents constant stress on transistors by evenly distributing the stress through the interconnection resources. By observing the impact of the signal probability on the aging of routing buffers, we enhance the synthesis flow as well as augment the proposed routing algorithm to converge the signal probabilities toward aging-friendly values. Experimental results over a set of industrial benchmarks and commerciallike FPGA architecture indicate the effectiveness of the proposed method with 64.3% reduction of stress duration in multiplexers and up to 45.2% improvement of the degradation of buffers. Altogether, the proposed method reduces the timing guardband by from 14.1% to 31.7%, depending on the FPGA routing architecture.

[1]  Vaughn Betz,et al.  Timing-driven placement for FPGAs , 2000, FPGA '00.

[2]  Kaushik Roy,et al.  Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Vaughn Betz,et al.  The Stratix II logic and routing architecture , 2005, FPGA '05.

[4]  Jim Tørresen,et al.  The Xilinx Design Language (XDL): Tutorial and use cases , 2011, 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC).

[5]  T. Knight,et al.  Pathfinder : A Negotiation-Based Performance-Driven Router for FPGAs , 2012 .

[6]  Mingjie Lin,et al.  Performance Benefits of Monolithically Stacked 3-D FPGA , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Marco Platzner,et al.  Design and architectures for dependable embedded systems , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[8]  Peter Y. K. Cheung,et al.  Modelling degradation in FPGA lookup tables , 2009, 2009 International Conference on Field-Programmable Technology.

[9]  Bishop Brock,et al.  Active management of timing guardband to save energy in POWER7 , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[10]  Hossein Asadi,et al.  Chapter Seven - Introduction to Emerging SRAM-Based FPGA Architectures in Dark Silicon Era , 2018, Adv. Comput..

[11]  Kenneth B. Kent,et al.  Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research , 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

[12]  Jörg Henkel,et al.  Stress-aware routing to mitigate aging effects in SRAM-based FPGAs , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

[13]  Abdulazim Amouri,et al.  Altering LUT configuration for wear-out mitigation of FPGA-mapped designs , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[14]  Jörg Henkel,et al.  Reliability-aware design to suppress aging , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[15]  Hossein Asadi,et al.  A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[16]  Erika Gunadi,et al.  Combating Aging with the Colt Duty Cycle Equalizer , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[17]  Abdulazim Amouri,et al.  Investigation of aging effects in different implementations and structures of programmable routing resources of FPGAs , 2012, 2012 International Conference on Field-Programmable Technology.

[18]  Fabian Vargas,et al.  Design and Validation of Configurable Online Aging Sensors in Nanometer-Scale FPGAs , 2013, IEEE Transactions on Nanotechnology.

[19]  Jörg Henkel,et al.  Connecting the physical and application level towards grasping aging effects , 2015, 2015 IEEE International Reliability Physics Symposium.

[20]  Jörg Henkel,et al.  STRAP: Stress-aware placement for aging mitigation in runtime reconfigurable architectures , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[21]  X. Federspiel,et al.  Microscopic scale characterization and modeling of transistor degradation under HC stress , 2012, Microelectron. Reliab..

[22]  Sen Wang,et al.  VTR 7.0: Next Generation Architecture and CAD System for FPGAs , 2014, TRETS.

[23]  Nader Bagherzadeh,et al.  STABLE: Stress-Aware Boolean Matching to Mitigate BTI-Induced SNM Reduction in SRAM-Based FPGAs , 2018, IEEE Transactions on Computers.

[24]  John Keane,et al.  An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB , 2010, IEEE Journal of Solid-State Circuits.

[25]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[26]  M.B. Tahoori,et al.  Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems , 2007, IEEE Transactions on Nuclear Science.

[27]  Mehdi Baradaran Tahoori,et al.  Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[28]  Yunsup Lee,et al.  The RISC-V Instruction Set Manual , 2014 .

[29]  Jörg Henkel,et al.  RESI: Register-Embedded Self-Immunity for Reliability Enhancement , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[30]  Peter Y. K. Cheung,et al.  Degradation Analysis and Mitigation in FPGAs , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[31]  Jonathan Rose,et al.  Measuring the Gap Between FPGAs and ASICs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[32]  S. Mahapatra,et al.  A consistent physical framework for N and P BTI in HKMG MOSFETs , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[33]  Brent E. Nelson,et al.  RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[34]  François Marc,et al.  Modelling delay degradation due to NBTI in FPGA Look-up tables , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

[35]  Vaughn Betz,et al.  Should FPGAS abandon the pass-gate? , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[36]  Hossein Asadi,et al.  PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era , 2017, IEEE Transactions on Computers.

[37]  Jörg Henkel,et al.  Towards interdependencies of aging mechanisms , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[38]  Siavash Bayat Sarmadi,et al.  FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic , 2015, IEEE Embedded Systems Letters.

[39]  Steven J. E. Wilton,et al.  Activity Estimation for Field-Programmable Gate Arrays , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[40]  Narayanan Vijaykrishnan,et al.  Toward Increasing FPGA Lifetime , 2008, IEEE Transactions on Dependable and Secure Computing.

[41]  Vaughn Betz,et al.  Automatic circuit design and modelling for heterogeneous FPGAs , 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

[42]  Muhammad Ashraful Alam,et al.  A comprehensive model of PMOS NBTI degradation , 2005, Microelectron. Reliab..

[43]  Sachin S. Sapatnekar,et al.  NBTI-Aware Synthesis of Digital Circuits , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[44]  Jörg Henkel,et al.  Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures , 2013, 2013 IEEE International Test Conference (ITC).